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ADC/DAC Conversion & Quantization (Electronics Engineering) Solved Questions & Notes (2026) - Apex Rankers

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ADC/DAC Conversion & Quantization

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Q. 1 Electronics Engineering
Difficulty: easy (1 Mark)
According to the Nyquist-Shannon Sampling Theorem, what is the minimum sampling frequency $f_s$ required to perfectly reconstruct a band-limited continuous analog signal with maximum frequency component $f_{max}$?
A
$f_s \ge f_{max}$
B
$f_s \ge 2 f_{max}$ (the Nyquist Rate)
✓ Correct
C
$f_s \ge 4 f_{max}$
D
$f_s = \frac{f_{max}}{2}$
💡 Step-by-Step Explanation & Concept Rationale
The sampling theorem states that a continuous band-limited signal can be completely reconstructed without aliasing if and only if the sampling rate is at least twice the highest frequency component present in the signal ($f_s \ge 2 f_{max}$).
Q. 2 Electronics Engineering
Difficulty: easy (1 Mark)
What is 'Aliasing' in digital signal processing, and how is it prevented in data acquisition systems?
A
The distortion caused by insufficient power supply voltage
B
The delay between sampling and conversion
C
High-frequency components above the Nyquist frequency ($f > f_s/2$) fold back into the baseband spectrum as false low-frequency artifacts; prevented by placing an analog Low-Pass Anti-Aliasing Filter before the ADC
✓ Correct
D
The loss of bits during serial transmission
💡 Step-by-Step Explanation & Concept Rationale
Frequencies exceeding $f_s/2$ create alias frequencies $|f - k f_s|$ that overlap indistinguishably with legitimate baseband signals; a steep analog low-pass filter must attenuate all signals above $f_s/2$ prior to sampling.
Q. 3 Electronics Engineering
Difficulty: medium (1 Mark)
What is the theoretical maximum Signal-to-Quantization-Noise Ratio (SQNR) for an ideal $N$-bit Analog-to-Digital Converter sampled with a full-scale sinusoidal input?
A
$\text{SQNR} = 20 \log_{10}(N)\text{ dB}$
B
$\text{SQNR} = 6.02 N\text{ dB}$
C
$\text{SQNR} = 6.02 N + 1.76\text{ dB}$
✓ Correct
D
$\text{SQNR} = 10 N + 3.01\text{ dB}$
💡 Step-by-Step Explanation & Concept Rationale
Assuming uniform quantization noise variance $\sigma_q^2 = \frac{q^2}{12}$ over the interval $[-q/2, +q/2]$, the root-mean-square signal to noise ratio evaluates to $\text{SNR} = 20\log_{10}(2^N) + 10\log_{10}(1.5) = 6.02 N + 1.76\text{ dB}$.
Q. 4 Electronics Engineering
Difficulty: easy (1 Mark)
What is the Voltage resolution of 1 Least Significant Bit (LSB) for a 12-bit ADC with a reference voltage $V_{REF} = 3.300\text{ V}$?
A
$\text{LSB} = 3.300\text{ V} \times 12 \approx 39.6\text{ mV}$
B
$\text{LSB} = 0.0806\text{ mV}$
C
$\text{LSB} = \frac{3.300\text{ V}}{4096} \approx 0.806\text{ mV}$
✓ Correct
D
$\text{LSB} = \frac{3.300\text{ V}}{1024} \approx 3.22\text{ mV}$
💡 Step-by-Step Explanation & Concept Rationale
For an $N$-bit ADC, the step size corresponding to 1 LSB is $\frac{V_{REF}}{2^N}$. For $N=12$, $2^{12} = 4096$, so $\text{LSB} = \frac{3.300\text{ V}}{4096} = 0.80566\text{ mV} \approx 806\text{ }\mu\text{V}$.
Q. 5 Electronics Engineering
Difficulty: medium (1 Mark)
How many precision analog voltage comparators are required in an $N$-bit Flash (Parallel) ADC architecture?
A
$2N + 1$
B
$2^N - 1$
✓ Correct
C
$2^N$
D
$N$
💡 Step-by-Step Explanation & Concept Rationale
A Flash ADC uses a resistive voltage divider with $2^N$ matched resistors and $2^N - 1$ comparators comparing the analog input simultaneously against all reference ladder levels in parallel within a single clock cycle.
Q. 6 Electronics Engineering
Difficulty: medium (1 Mark)
What are the primary operational characteristics and trade-offs of a Flash ADC?
A
Zero silicon area with lowest cost
B
Slow conversion requiring $N$ clock cycles per sample
C
Ultra-high conversion speed (gigabits per second, single-cycle latency), but exponential hardware complexity ($2^N-1$ comparators), high power dissipation, and high input capacitance, limiting practical resolution to 6-8 bits
✓ Correct
D
Highest resolution (24 bits) with lowest power dissipation
💡 Step-by-Step Explanation & Concept Rationale
Because hardware grows exponentially ($2^N - 1$), an 8-bit flash ADC needs 255 comparators, while a 16-bit flash would require 65,535 comparators, making flash ADCs practical only for ultra-fast, lower-resolution RF/oscilloscope front-ends.
Q. 7 Electronics Engineering
Difficulty: easy (1 Mark)
How does a Successive Approximation Register (SAR) ADC determine the digital output code for an analog input voltage?
A
It uses a Binary Search algorithm: testing bits from Most Significant Bit (MSB) down to LSB in $N$ clock cycles, comparing the input against the internal DAC output at each step
✓ Correct
B
It counts clock pulses until a ramp voltage equals the input voltage
C
It integrates input voltage over a fixed time period using an op-amp integrator
D
It samples $2^N - 1$ comparators simultaneously in parallel
💡 Step-by-Step Explanation & Concept Rationale
A SAR ADC operates like a binary balance scale: it sets the MSB to 1, checks the comparator output, keeps the bit if input is larger (or clears it if smaller), and repeats sequentially for all $N$ bits in exactly $N$ clock cycles.
Q. 8 Electronics Engineering
Difficulty: medium (1 Mark)
Why is an external or integrated 'Sample-and-Hold' (S/H or Track-and-Hold) amplifier circuit mandatory at the front-end of a SAR ADC?
A
To convert differential voltage into single-ended current
B
To filter out 50 Hz power line noise
C
To amplify the signal by a factor of 1000
D
To hold the sampled input voltage constant and steady on an internal capacitor while the SAR sequencer performs its multi-clock binary search conversion
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
If the analog input changes by more than 0.5 LSB during the $N$ clock cycles of SAR bit testing, the binary search algorithm fails and generates massive conversion errors; the S/H freezes the voltage during conversion.
Q. 9 Electronics Engineering
Difficulty: medium (1 Mark)
What are the defining characteristics of a Sigma-Delta ($\Delta\Sigma$ or $\Sigma\Delta$) ADC?
A
High-frequency Oversampling ($f_s \gg 2 f_{max}$), Noise Shaping (pushing quantization noise to high out-of-band frequencies), and a Digital Decimation Sinc Filter, delivering ultra-high resolution (16 to 24+ bits) for low-to-medium bandwidth signals
✓ Correct
B
Single-cycle conversion with $2^N-1$ comparators
C
Binary search using a resistive ladder in $N$ clock cycles
D
Dual-slope integration with zero oversampling
💡 Step-by-Step Explanation & Concept Rationale
Sigma-Delta ADCs use an analog feedback loop with an integrator to shape quantization noise, shifting noise power into high frequencies where digital low-pass decimation filters eliminate it, achieving 24-bit precision for seismic/biomedical/audio sensing.
Q. 10 Electronics Engineering
Difficulty: hard (1 Mark)
What is 'Noise Shaping' in Sigma-Delta modulation?
A
Reducing the analog input voltage to zero
B
Shaping the physical noise wave using an acoustic horn
C
A technique for smoothing power supply ripple
D
The integrator feedback loop acts as a low-pass filter for the input signal and a high-pass filter for the quantization noise, pushing quantization noise power out of the low-frequency signal band into high frequencies
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
By placing the 1-bit quantizer inside a feedback loop with an integrator, the transfer function for quantization noise becomes $H_N(z) = 1 - z^{-1}$ (a first-order high-pass differentiator), relocating noise away from DC/baseband.
Q. 11 Electronics Engineering
Difficulty: medium (1 Mark)
What is the 'Oversampling Ratio' (OSR) in Sigma-Delta ADC architecture?
A
$\text{OSR} = \frac{f_s}{2 f_{Nyquist}} = \frac{f_s}{2 f_B}$ (the ratio of the actual sampling frequency to the Nyquist rate)
✓ Correct
B
$\text{OSR} = 2^N$
C
$\text{OSR} = \frac{V_{REF}}{\text{LSB}}$
D
$\text{OSR} = f_s \times 2 f_B$
💡 Step-by-Step Explanation & Concept Rationale
Oversampling spreads the fixed total quantization noise power $\sigma_q^2 = q^2/12$ over a wider bandwidth $f_s/2$; doubling the OSR in a 1st-order sigma-delta modulator improves SNR by 9 dB (1.5 bits of resolution).
Q. 12 Electronics Engineering
Difficulty: hard (1 Mark)
How does a Dual-Slope (Integrating) ADC achieve exceptional rejection of 50 Hz and 60 Hz power-line AC noise?
A
By cooling the integrator capacitor to sub-zero temperatures
B
By using high-speed optical isolators
C
By converting AC noise into DC voltage
D
By setting the run-up integration time $T_1$ to be an exact integer multiple of the power-line period ($T_1 = k \times 20\text{ ms}$ for 50 Hz, $k \times 16.67\text{ ms}$ for 60 Hz), causing the integral of the sinusoidal noise to evaluate to exactly zero
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Integrating a periodic sine wave over its exact period $\int_0^T \sin(\omega t) dt = 0$ yields mathematically zero average noise contribution, giving dual-slope ADCs (used in digital multimeters) $>60\text{ dB}$ normal-mode line rejection.
Q. 13 Electronics Engineering
Difficulty: medium (1 Mark)
In a Dual-Slope ADC, what is the mathematical relationship between input voltage $V_{in}$, reference voltage $V_{REF}$, fixed run-up time $T_1$, and measured run-down discharge time $T_2$?
A
$V_{in} = V_{REF} \times \frac{T_2}{T_1}$
✓ Correct
B
$V_{in} = V_{REF} \times \frac{T_1}{T_2}$
C
$V_{in} = V_{REF} \times R C$
D
$V_{in} = \frac{R C}{T_1 T_2}$
💡 Step-by-Step Explanation & Concept Rationale
During run-up: $\Delta V = \frac{V_{in} T_1}{RC}$. During run-down: $\Delta V = \frac{V_{REF} T_2}{RC}$. Equating the two cancels out component values $R$ and $C$ as well as clock frequency drift: $V_{in} = V_{REF} \frac{T_2}{T_1}$.
Q. 14 Electronics Engineering
Difficulty: medium (1 Mark)
What is the primary operational advantage of the Dual-Slope ADC equation $V_{in} = V_{REF} \frac{T_2}{T_1}$?
A
It can sample at 100 Megasamples per second
B
The measurement accuracy is completely independent of the exact capacitance $C$, resistance $R$, and clock oscillator frequency drift, depending only on the stability of $V_{REF}$ and ratio of digital counts
✓ Correct
C
It uses zero power supply current
D
It requires no reference voltage
💡 Step-by-Step Explanation & Concept Rationale
Because $R$, $C$, and clock frequency $f_{clk}$ appear in both run-up and run-down phases, long-term component drift cancels out mathematically, delivering excellent temperature stability and linearity in lab multimeters.
Q. 15 Electronics Engineering
Difficulty: medium (1 Mark)
What is a 'Pipeline ADC' architecture?
A
An ADC that measures the pressure of water flowing in a pipeline
B
An ADC that cascades multiple low-resolution flash sub-stages separated by sample-and-hold amplifiers, digitizing an analog sample in pipeline stages to achieve high throughput (e.g., 100 MSPS) with 12-16 bit resolution
✓ Correct
C
An ADC with a single comparator and an up-counter
D
A software simulation of an analog converter
💡 Step-by-Step Explanation & Concept Rationale
Pipeline ADCs process samples concurrently in pipeline stages: while stage 1 digitizes sample $N$, stage 2 processes residual of sample $N-1$, yielding high throughput (1 sample per clock) with a fixed pipeline latency.
Q. 16 Electronics Engineering
Difficulty: easy (1 Mark)
What is Differential Non-Linearity (DNL) in ADC and DAC specifications?
A
The ratio of harmonic distortion to fundamental signal
B
The deviation of the transfer curve from a straight line connecting endpoints
C
The difference between the actual measured step width between two adjacent code transitions and the ideal physical step width of 1 LSB: $\text{DNL} = \frac{\text{Actual Step} - \text{Ideal LSB}}{\text{Ideal LSB}}$
✓ Correct
D
The temperature drift of the internal bandgap reference
💡 Step-by-Step Explanation & Concept Rationale
DNL measures step uniformity: an ideal converter has $\text{DNL} = 0\text{ LSB}$. If $\text{DNL} < -1.0\text{ LSB}$, the ADC exhibits 'Missing Codes' (or non-monotonicity in a DAC).
Q. 17 Electronics Engineering
Difficulty: medium (1 Mark)
What occurs in an Analog-to-Digital Converter if its Differential Non-Linearity is strictly less than $-1.0\text{ LSB}$ ($\text{DNL} < -1.0\text{ LSB}$)?
A
The ADC explodes due to overvoltage
B
The ADC output is inverted
C
The ADC becomes 100% efficient
D
The ADC suffers from 'Missing Codes' (certain digital output codes can never be produced for any analog input voltage)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
A transition width of less than $0\text{ LSB}$ ($\text{DNL} < -1$) means the code transition point has crossed over its neighbor, skipping that code completely and creating a permanent missing code.
Q. 18 Electronics Engineering
Difficulty: easy (1 Mark)
What is 'Monotonicity' in a Digital-to-Analog Converter (DAC)?
A
A DAC that operates with a single supply rail
B
A property where the analog output voltage strictly increases (or stays constant) as the input digital code increases, guaranteeing $\text{DNL} \ge -1.0\text{ LSB}$
✓ Correct
C
A DAC that outputs only a single constant DC voltage
D
A DAC that produces a monotone audible beep
💡 Step-by-Step Explanation & Concept Rationale
A non-monotonic DAC exhibits a dangerous glitch where incrementing the digital code causes the analog output voltage to step downwards, destabilizing closed-loop control systems.
Q. 19 Electronics Engineering
Difficulty: medium (1 Mark)
What is Integral Non-Linearity (INL) in ADC and DAC performance?
A
The maximum deviation of the actual transfer function curve from the ideal straight reference line (Best-Fit line or End-Point line) after correcting for offset and gain errors
✓ Correct
B
The difference between the first and last digital code
C
The power consumption of the internal voltage reference
D
The ratio of input impedance to output impedance
💡 Step-by-Step Explanation & Concept Rationale
INL represents the cumulative sum of DNL errors across the full dynamic range, measuring the overall curvature and distortion of the conversion transfer curve.
Q. 20 Electronics Engineering
Difficulty: medium (1 Mark)
What is the 'Effective Number of Bits' (ENOB) defined as in terms of Signal-to-Noise and Distortion (SINAD)?
A
$\text{ENOB} = 2^N - 1$
B
$\text{ENOB} = \frac{\text{SINAD}}{6.02}$
C
$\text{ENOB} = \text{SINAD} \times 6.02 + 1.76$
D
$\text{ENOB} = \frac{\text{SINAD} - 1.76\text{ dB}}{6.02}$
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
ENOB accounts for all real-world converter imperfections (quantization noise, thermal noise, harmonic distortion, clock jitter): $\text{ENOB} = \frac{\text{SINAD}(\text{dB}) - 1.76}{6.02}$. A real 16-bit ADC may have an ENOB of 14.2 bits.
Q. 21 Electronics Engineering
Difficulty: hard (1 Mark)
What is 'Spurious-Free Dynamic Range' (SFDR) of an ADC?
A
The ratio (in dBc or dBFS) of the RMS amplitude of the fundamental input signal to the RMS amplitude of the single largest spurious or harmonic distortion peak in the output spectrum
✓ Correct
B
The range of frequencies where the ADC operates with zero power
C
The ratio of sample rate to signal bandwidth
D
The difference between maximum and minimum DC input voltage
💡 Step-by-Step Explanation & Concept Rationale
SFDR measures the converter's ability to distinguish a weak target signal in the presence of strong interfering tones without spur peaks obscuring the detection threshold in radar/SDR applications.
Q. 22 Electronics Engineering
Difficulty: easy (1 Mark)
What is 'Total Harmonic Distortion' (THD) of an analog converter?
A
The ratio of the sum of the powers of all harmonic distortion components to the power of the fundamental frequency: $\text{THD} = \frac{\sqrt{V_2^2 + V_3^2 + V_4^2 + \dots}}{V_1}$
✓ Correct
B
The noise floor of the ADC in microvolts
C
The total power dissipated as heat in the chip
D
The maximum phase shift introduced by the anti-aliasing filter
💡 Step-by-Step Explanation & Concept Rationale
THD quantifies non-linear distortion generated by converter transfer curve non-linearities, expressed in dB or percentage relative to the fundamental signal amplitude.
Q. 23 Electronics Engineering
Difficulty: hard (1 Mark)
What is 'Aperture Jitter' (Aperture Uncertainty, $\sigma_{t_j}$) in sample-and-hold and ADC circuits?
A
Thermal expansion of the silicon die during high-power operation
B
The delay in reading the digital output bus
C
Sample-to-sample timing variations (phase noise / clock jitter) in the exact instant when the sample-and-hold switch opens, converting timing uncertainty into amplitude voltage error: $\Delta V = \left.\frac{dV}{dt}\right|_{max} \sigma_{t_j}$
✓ Correct
D
The physical opening width of an optical camera lens
💡 Step-by-Step Explanation & Concept Rationale
For a fast sine wave $V(t) = A\sin(2\pi f t)$, maximum slew rate is $2\pi f A$. Aperture jitter $\sigma_{t_j}$ introduces amplitude noise that caps maximum SNR: $\text{SNR}_{jitter} = -20\log_{10}(2\pi f_{in} \sigma_{t_j})$.
Q. 24 Electronics Engineering
Difficulty: hard (1 Mark)
What is the maximum analog input frequency $f_{max}$ that an ideal 16-bit ADC can digitize with less than 0.5 LSB error if clock aperture jitter is $\sigma_{t_j} = 1\text{ picosecond}$ ($10^{-12}\text{ s}$)?
A
$f_{max} = 1\text{ GHz}$
B
$f_{max} = \frac{1}{2\pi \sigma_{t_j} 2^N} = \frac{1}{2\pi \times 10^{-12} \times 65536} \approx 2.43\text{ MHz}$
✓ Correct
C
$f_{max} = 100\text{ kHz}$
D
$f_{max} = 50\text{ MHz}$
💡 Step-by-Step Explanation & Concept Rationale
Using $f_{max} = \frac{1}{2\pi \sigma_t 2^N} = \frac{1}{2\pi \times 10^{-12} \times 65,536} = \frac{1}{4.117 \times 10^{-7}} \approx 2.43\text{ MHz}$. High resolution at high frequencies demands sub-picosecond low-jitter clocks.
Q. 25 Electronics Engineering
Difficulty: easy (1 Mark)
What is the R-2R Ladder Digital-to-Analog Converter (DAC) architecture and why is it preferred over Binary-Weighted resistor DACs?
A
It requires no operational amplifier at the output
B
It uses a ladder network consisting of only two precision resistor values ($R$ and $2R$), eliminating the wide range of resistor values needed in binary-weighted DACs and ensuring excellent thermal tracking and ease of monolithic IC fabrication
✓ Correct
C
It uses 100 different resistor values to improve precision
D
It operates only on AC audio signals
💡 Step-by-Step Explanation & Concept Rationale
Binary-weighted DACs need resistor ratios up to $2^N:1$ (e.g., $1\text{ k}\Omega$ to $65.5\text{ M}\Omega$ for 16-bit), which is impossible to match on silicon; R-2R ladders need only $R$ and $2R$ matching pairs.
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