ADC/DAC Conversion & Quantization
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📘 Comprehensive Syllabus & Examination Guide
ADC/DAC Conversion & Quantization
Official curriculum roadmap, subject/topic distribution, negative marking rules, pacing guidelines, and solved sample questions.
🎯 Mapped Subjects & Topic Question Distribution
Total Question Pool
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61 MCQs
Combined Active Syllabus
ADC/DAC Conversion & Quantization
61 MCQs
Topic Pool
📊 Question Pool Structure
61 MCQs across fundamental, intermediate, and advanced concept tiers.
⚡ Recommended Pacing
45 to 60 seconds per MCQ. Flag complex problems and preserve 10 minutes for final revision.
⚖️ Scoring & Negative Marking
+1 mark per correct answer. In competitive tests with negative marking, -0.25 applies for incorrect guesses.
💡 Strategic Preparation & Exam Hall Guidelines
To maximize your score on ADC/DAC Conversion & Quantization, candidates are advised to follow a structured three-pass approach. In the First Pass, solve all direct recall and formula-based questions within 30 seconds each to secure foundational marks. In the Second Pass, tackle multi-step analytical and quantitative reasoning problems. In the Third Pass, review marked questions and verify calculations.
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📝 Pre-Rendered Solved Sample Questions & Detailed Solutions
Review the solved problems below to understand question phrasing, answer choices, and step-by-step solution logic prior to starting the full interactive practice drill:
Sample Question 1
ADC/DAC Conversion & Quantization
easy • Electronics Engineering
According to the Nyquist-Shannon Sampling Theorem, what is the minimum sampling frequency $f_s$ required to perfectly reconstruct a band-limited continuous analog signal with maximum frequency component $f_{max}$?
A
$f_s \ge f_{max}$
B
$f_s \ge 2 f_{max}$ (the Nyquist Rate)
C
$f_s \ge 4 f_{max}$
D
$f_s = \frac{f_{max}}{2}$
✓ Correct Answer: B - $f_s \ge 2 f_{max}$ (the Nyquist Rate)
📖 Step-by-Step Solution & Conceptual Rationale:
The sampling theorem states that a continuous band-limited signal can be completely reconstructed without aliasing if and only if the sampling rate is at least twice the highest frequency component present in the signal ($f_s \ge 2 f_{max}$).
Sample Question 2
ADC/DAC Conversion & Quantization
easy • Electronics Engineering
What is 'Aliasing' in digital signal processing, and how is it prevented in data acquisition systems?
A
The distortion caused by insufficient power supply voltage
B
The delay between sampling and conversion
C
High-frequency components above the Nyquist frequency ($f > f_s/2$) fold back into the baseband spectrum as false low-frequency artifacts; prevented by placing an analog Low-Pass Anti-Aliasing Filter before the ADC
D
The loss of bits during serial transmission
✓ Correct Answer: C - High-frequency components above the Nyquist frequency ($f > f_s/2$) fold back into the baseband spectrum as false low-frequency artifacts; prevented by placing an analog Low-Pass Anti-Aliasing Filter before the ADC
📖 Step-by-Step Solution & Conceptual Rationale:
Frequencies exceeding $f_s/2$ create alias frequencies $|f - k f_s|$ that overlap indistinguishably with legitimate baseband signals; a steep analog low-pass filter must attenuate all signals above $f_s/2$ prior to sampling.
Sample Question 3
ADC/DAC Conversion & Quantization
medium • Electronics Engineering
What is the theoretical maximum Signal-to-Quantization-Noise Ratio (SQNR) for an ideal $N$-bit Analog-to-Digital Converter sampled with a full-scale sinusoidal input?
A
$\text{SQNR} = 20 \log_{10}(N)\text{ dB}$
B
$\text{SQNR} = 6.02 N\text{ dB}$
C
$\text{SQNR} = 6.02 N + 1.76\text{ dB}$
D
$\text{SQNR} = 10 N + 3.01\text{ dB}$
✓ Correct Answer: C - $\text{SQNR} = 6.02 N + 1.76\text{ dB}$
📖 Step-by-Step Solution & Conceptual Rationale:
Assuming uniform quantization noise variance $\sigma_q^2 = \frac{q^2}{12}$ over the interval $[-q/2, +q/2]$, the root-mean-square signal to noise ratio evaluates to $\text{SNR} = 20\log_{10}(2^N) + 10\log_{10}(1.5) = 6.02 N + 1.76\text{ dB}$.
Sample Question 4
ADC/DAC Conversion & Quantization
easy • Electronics Engineering
What is the Voltage resolution of 1 Least Significant Bit (LSB) for a 12-bit ADC with a reference voltage $V_{REF} = 3.300\text{ V}$?
A
$\text{LSB} = 3.300\text{ V} \times 12 \approx 39.6\text{ mV}$
B
$\text{LSB} = 0.0806\text{ mV}$
C
$\text{LSB} = \frac{3.300\text{ V}}{4096} \approx 0.806\text{ mV}$
D
$\text{LSB} = \frac{3.300\text{ V}}{1024} \approx 3.22\text{ mV}$
✓ Correct Answer: C - $\text{LSB} = \frac{3.300\text{ V}}{4096} \approx 0.806\text{ mV}$
📖 Step-by-Step Solution & Conceptual Rationale:
For an $N$-bit ADC, the step size corresponding to 1 LSB is $\frac{V_{REF}}{2^N}$. For $N=12$, $2^{12} = 4096$, so $\text{LSB} = \frac{3.300\text{ V}}{4096} = 0.80566\text{ mV} \approx 806\text{ }\mu\text{V}$.
Sample Question 5
ADC/DAC Conversion & Quantization
medium • Electronics Engineering
How many precision analog voltage comparators are required in an $N$-bit Flash (Parallel) ADC architecture?
A
$2N + 1$
B
$2^N - 1$
C
$2^N$
D
$N$
✓ Correct Answer: B - $2^N - 1$
📖 Step-by-Step Solution & Conceptual Rationale:
A Flash ADC uses a resistive voltage divider with $2^N$ matched resistors and $2^N - 1$ comparators comparing the analog input simultaneously against all reference ladder levels in parallel within a single clock cycle.
Sample Question 6
ADC/DAC Conversion & Quantization
medium • Electronics Engineering
What are the primary operational characteristics and trade-offs of a Flash ADC?
A
Zero silicon area with lowest cost
B
Slow conversion requiring $N$ clock cycles per sample
C
Ultra-high conversion speed (gigabits per second, single-cycle latency), but exponential hardware complexity ($2^N-1$ comparators), high power dissipation, and high input capacitance, limiting practical resolution to 6-8 bits
D
Highest resolution (24 bits) with lowest power dissipation
✓ Correct Answer: C - Ultra-high conversion speed (gigabits per second, single-cycle latency), but exponential hardware complexity ($2^N-1$ comparators), high power dissipation, and high input capacitance, limiting practical resolution to 6-8 bits
📖 Step-by-Step Solution & Conceptual Rationale:
Because hardware grows exponentially ($2^N - 1$), an 8-bit flash ADC needs 255 comparators, while a 16-bit flash would require 65,535 comparators, making flash ADCs practical only for ultra-fast, lower-resolution RF/oscilloscope front-ends.
Sample Question 7
ADC/DAC Conversion & Quantization
easy • Electronics Engineering
How does a Successive Approximation Register (SAR) ADC determine the digital output code for an analog input voltage?
A
It uses a Binary Search algorithm: testing bits from Most Significant Bit (MSB) down to LSB in $N$ clock cycles, comparing the input against the internal DAC output at each step
B
It counts clock pulses until a ramp voltage equals the input voltage
C
It integrates input voltage over a fixed time period using an op-amp integrator
D
It samples $2^N - 1$ comparators simultaneously in parallel
✓ Correct Answer: A - It uses a Binary Search algorithm: testing bits from Most Significant Bit (MSB) down to LSB in $N$ clock cycles, comparing the input against the internal DAC output at each step
📖 Step-by-Step Solution & Conceptual Rationale:
A SAR ADC operates like a binary balance scale: it sets the MSB to 1, checks the comparator output, keeps the bit if input is larger (or clears it if smaller), and repeats sequentially for all $N$ bits in exactly $N$ clock cycles.
Sample Question 8
ADC/DAC Conversion & Quantization
medium • Electronics Engineering
Why is an external or integrated 'Sample-and-Hold' (S/H or Track-and-Hold) amplifier circuit mandatory at the front-end of a SAR ADC?
A
To convert differential voltage into single-ended current
B
To filter out 50 Hz power line noise
C
To amplify the signal by a factor of 1000
D
To hold the sampled input voltage constant and steady on an internal capacitor while the SAR sequencer performs its multi-clock binary search conversion
✓ Correct Answer: D - To hold the sampled input voltage constant and steady on an internal capacitor while the SAR sequencer performs its multi-clock binary search conversion
📖 Step-by-Step Solution & Conceptual Rationale:
If the analog input changes by more than 0.5 LSB during the $N$ clock cycles of SAR bit testing, the binary search algorithm fails and generates massive conversion errors; the S/H freezes the voltage during conversion.
Sample Question 9
ADC/DAC Conversion & Quantization
medium • Electronics Engineering
What are the defining characteristics of a Sigma-Delta ($\Delta\Sigma$ or $\Sigma\Delta$) ADC?
A
High-frequency Oversampling ($f_s \gg 2 f_{max}$), Noise Shaping (pushing quantization noise to high out-of-band frequencies), and a Digital Decimation Sinc Filter, delivering ultra-high resolution (16 to 24+ bits) for low-to-medium bandwidth signals
B
Single-cycle conversion with $2^N-1$ comparators
C
Binary search using a resistive ladder in $N$ clock cycles
D
Dual-slope integration with zero oversampling
✓ Correct Answer: A - High-frequency Oversampling ($f_s \gg 2 f_{max}$), Noise Shaping (pushing quantization noise to high out-of-band frequencies), and a Digital Decimation Sinc Filter, delivering ultra-high resolution (16 to 24+ bits) for low-to-medium bandwidth signals
📖 Step-by-Step Solution & Conceptual Rationale:
Sigma-Delta ADCs use an analog feedback loop with an integrator to shape quantization noise, shifting noise power into high frequencies where digital low-pass decimation filters eliminate it, achieving 24-bit precision for seismic/biomedical/audio sensing.
Sample Question 10
ADC/DAC Conversion & Quantization
hard • Electronics Engineering
What is 'Noise Shaping' in Sigma-Delta modulation?
A
Reducing the analog input voltage to zero
B
Shaping the physical noise wave using an acoustic horn
C
A technique for smoothing power supply ripple
D
The integrator feedback loop acts as a low-pass filter for the input signal and a high-pass filter for the quantization noise, pushing quantization noise power out of the low-frequency signal band into high frequencies
✓ Correct Answer: D - The integrator feedback loop acts as a low-pass filter for the input signal and a high-pass filter for the quantization noise, pushing quantization noise power out of the low-frequency signal band into high frequencies
📖 Step-by-Step Solution & Conceptual Rationale:
By placing the 1-bit quantizer inside a feedback loop with an integrator, the transfer function for quantization noise becomes $H_N(z) = 1 - z^{-1}$ (a first-order high-pass differentiator), relocating noise away from DC/baseband.
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