Q. 1
Electronics Engineering
Difficulty: Easy
(1 Mark)
In the Intel 8085 microprocessor, what is the width of the data bus and address bus respectively?
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Step-by-Step Explanation & Concept Rationale
The 8085 is an 8-bit microprocessor with an 8-bit multiplexed data bus (AD0-AD7) and a 16-bit address bus (A8-A15 and AD0-AD7), capable of addressing 2^16 = 64 KB of memory.
Q. 2
Electronics Engineering
Difficulty: Easy
(1 Mark)
In the 8085 microprocessor, which pin is used to demultiplex the lower-order address/data bus (AD0-AD7)?
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Step-by-Step Explanation & Concept Rationale
ALE (Address Latch Enable) is a positive-going pulse emitted during clock cycle T1 of a machine cycle to latch the lower 8-bit address into an external 74LS373 latch.
Q. 3
Electronics Engineering
Difficulty: Easy
(1 Mark)
Among the hardware interrupts of the 8085 microprocessor, which interrupt is non-maskable and has the highest priority?
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Step-by-Step Explanation & Concept Rationale
TRAP (vectored at memory address 0024H) is the only non-maskable hardware interrupt in the 8085, both edge- and level-sensitive, and holds the highest priority.
Q. 4
Electronics Engineering
Difficulty: Easy
(1 Mark)
What is the memory addressing capacity of the Intel 8086 microprocessor with its 20-bit address bus?
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Step-by-Step Explanation & Concept Rationale
With a 20-bit address bus, the 8086 can directly address 2^20 = 1,048,576 bytes = 1 Megabyte (1 MB) of memory.
Q. 5
Electronics Engineering
Difficulty: Medium
(1 Mark)
In the 8086 microprocessor, how is a 20-bit physical memory address computed from Segment and Offset registers?
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Step-by-Step Explanation & Concept Rationale
The Bus Interface Unit (BIU) shifts the 16-bit Segment register left by 4 bits (multiplies by 10H or 16 decimal) and adds the 16-bit Offset to yield the 20-bit physical address.
Q. 6
Electronics Engineering
Difficulty: Medium
(1 Mark)
In an 8051 microcontroller, what is the default vector address for the external interrupt INT0?
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Step-by-Step Explanation & Concept Rationale
8051 interrupt vector addresses: Reset = 0000H, INT0 = 0003H, Timer 0 = 000BH, INT1 = 0013H, Timer 1 = 001BH, Serial Comm = 0023H.
Q. 7
Electronics Engineering
Difficulty: Easy
(1 Mark)
What is the fundamental architectural difference between Harvard architecture and von Neumann architecture?
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Step-by-Step Explanation & Concept Rationale
Harvard architecture features separate memory spaces and buses for program code and data, allowing simultaneous instruction fetch and data read/write. Von Neumann shares a unified memory bus (von Neumann bottleneck).
Q. 8
Electronics Engineering
Difficulty: Easy
(1 Mark)
In embedded systems, what is the function of a Watchdog Timer (WDT)?
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Step-by-Step Explanation & Concept Rationale
A watchdog timer is an autonomous hardware countdown timer that must be periodically cleared ('kicked') by software. If code hangs and fails to service it, the timer overflows and forces a system reset.
Q. 9
Electronics Engineering
Difficulty: Easy
(1 Mark)
Which serial communication protocol uses two bidirectional open-drain lines (SDA and SCL) with pull-up resistors and supports multi-master operation?
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Step-by-Step Explanation & Concept Rationale
I2C (invented by Philips/NXP) uses two wires: Serial Data (SDA) and Serial Clock (SCL), both pulled high by pull-up resistors, supporting addressing of multiple peripherals.
Q. 10
Electronics Engineering
Difficulty: Easy
(1 Mark)
Which serial interface is synchronous, full-duplex, and uses four lines: MOSI, MISO, SCK, and SS/CS?
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Step-by-Step Explanation & Concept Rationale
SPI operates with 4 signals: Master Out Slave In (MOSI), Master In Slave Out (MISO), Serial Clock (SCK), and Slave Select (SS), offering high data throughput with low protocol overhead.
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