Microprocessors & Embedded Systems
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📘 Comprehensive Syllabus & Examination Guide
Microprocessors & Embedded Systems
Official curriculum roadmap, subject/topic distribution, negative marking rules, pacing guidelines, and solved sample questions.
🎯 Mapped Subjects & Topic Question Distribution
Total Question Pool
100%
10 MCQs
Combined Active Syllabus
Microprocessors & Embedded Systems
10 MCQs
Topic Pool
📊 Question Pool Structure
10 MCQs across fundamental, intermediate, and advanced concept tiers.
⚡ Recommended Pacing
45 to 60 seconds per MCQ. Flag complex problems and preserve 10 minutes for final revision.
⚖️ Scoring & Negative Marking
+1 mark per correct answer. In competitive tests with negative marking, -0.25 applies for incorrect guesses.
💡 Strategic Preparation & Exam Hall Guidelines
To maximize your score on Microprocessors & Embedded Systems, candidates are advised to follow a structured three-pass approach. In the First Pass, solve all direct recall and formula-based questions within 30 seconds each to secure foundational marks. In the Second Pass, tackle multi-step analytical and quantitative reasoning problems. In the Third Pass, review marked questions and verify calculations.
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Showing 10 solved representative questions
📝 Pre-Rendered Solved Sample Questions & Detailed Solutions
Review the solved problems below to understand question phrasing, answer choices, and step-by-step solution logic prior to starting the full interactive practice drill:
Sample Question 1
Microprocessors & Embedded Systems
Easy • Electronics Engineering
In the Intel 8085 microprocessor, what is the width of the data bus and address bus respectively?
A
8-bit data bus and 16-bit address bus
B
16-bit data bus and 16-bit address bus
C
8-bit data bus and 8-bit address bus
D
16-bit data bus and 20-bit address bus
✓ Correct Answer: A - 8-bit data bus and 16-bit address bus
📖 Step-by-Step Solution & Conceptual Rationale:
The 8085 is an 8-bit microprocessor with an 8-bit multiplexed data bus (AD0-AD7) and a 16-bit address bus (A8-A15 and AD0-AD7), capable of addressing 2^16 = 64 KB of memory.
Sample Question 2
Microprocessors & Embedded Systems
Easy • Electronics Engineering
In the 8085 microprocessor, which pin is used to demultiplex the lower-order address/data bus (AD0-AD7)?
A
ALE (Address Latch Enable)
B
IO/M
C
RD (Read)
D
READY
✓ Correct Answer: A - ALE (Address Latch Enable)
📖 Step-by-Step Solution & Conceptual Rationale:
ALE (Address Latch Enable) is a positive-going pulse emitted during clock cycle T1 of a machine cycle to latch the lower 8-bit address into an external 74LS373 latch.
Sample Question 3
Microprocessors & Embedded Systems
Easy • Electronics Engineering
Among the hardware interrupts of the 8085 microprocessor, which interrupt is non-maskable and has the highest priority?
A
RST 7.5
B
TRAP
C
RST 6.5
D
INTR
✓ Correct Answer: B - TRAP
📖 Step-by-Step Solution & Conceptual Rationale:
TRAP (vectored at memory address 0024H) is the only non-maskable hardware interrupt in the 8085, both edge- and level-sensitive, and holds the highest priority.
Sample Question 4
Microprocessors & Embedded Systems
Easy • Electronics Engineering
What is the memory addressing capacity of the Intel 8086 microprocessor with its 20-bit address bus?
A
64 KB
B
1 MB
C
16 MB
D
4 GB
✓ Correct Answer: B - 1 MB
📖 Step-by-Step Solution & Conceptual Rationale:
With a 20-bit address bus, the 8086 can directly address 2^20 = 1,048,576 bytes = 1 Megabyte (1 MB) of memory.
Sample Question 5
Microprocessors & Embedded Systems
Medium • Electronics Engineering
In the 8086 microprocessor, how is a 20-bit physical memory address computed from Segment and Offset registers?
A
Physical Address = (Segment Register * 10H) + Offset
B
Physical Address = Segment Register + Offset
C
Physical Address = (Segment Register * 100H) + Offset
D
Physical Address = Segment Register * Offset
✓ Correct Answer: A - Physical Address = (Segment Register * 10H) + Offset
📖 Step-by-Step Solution & Conceptual Rationale:
The Bus Interface Unit (BIU) shifts the 16-bit Segment register left by 4 bits (multiplies by 10H or 16 decimal) and adds the 16-bit Offset to yield the 20-bit physical address.
Sample Question 6
Microprocessors & Embedded Systems
Medium • Electronics Engineering
In an 8051 microcontroller, what is the default vector address for the external interrupt INT0?
A
0003H
B
000BH
C
0013H
D
0023H
✓ Correct Answer: A - 0003H
📖 Step-by-Step Solution & Conceptual Rationale:
8051 interrupt vector addresses: Reset = 0000H, INT0 = 0003H, Timer 0 = 000BH, INT1 = 0013H, Timer 1 = 001BH, Serial Comm = 0023H.
Sample Question 7
Microprocessors & Embedded Systems
Easy • Electronics Engineering
What is the fundamental architectural difference between Harvard architecture and von Neumann architecture?
A
Harvard architecture has separate physical memories and buses for program instructions and data, whereas von Neumann shares memory and bus for both
B
Von Neumann architecture uses 64-bit registers only
C
Harvard architecture does not support subroutines
D
Von Neumann architecture cannot execute instructions sequentially
✓ Correct Answer: A - Harvard architecture has separate physical memories and buses for program instructions and data, whereas von Neumann shares memory and bus for both
📖 Step-by-Step Solution & Conceptual Rationale:
Harvard architecture features separate memory spaces and buses for program code and data, allowing simultaneous instruction fetch and data read/write. Von Neumann shares a unified memory bus (von Neumann bottleneck).
Sample Question 8
Microprocessors & Embedded Systems
Easy • Electronics Engineering
In embedded systems, what is the function of a Watchdog Timer (WDT)?
A
To keep track of real-world calendar date and time
B
To reset the microcontroller if the software enters an infinite loop or hangs due to a glitch
C
To measure the execution time of subroutines for profiling
D
To regulate input power supply voltage
✓ Correct Answer: B - To reset the microcontroller if the software enters an infinite loop or hangs due to a glitch
📖 Step-by-Step Solution & Conceptual Rationale:
A watchdog timer is an autonomous hardware countdown timer that must be periodically cleared ('kicked') by software. If code hangs and fails to service it, the timer overflows and forces a system reset.
Sample Question 9
Microprocessors & Embedded Systems
Easy • Electronics Engineering
Which serial communication protocol uses two bidirectional open-drain lines (SDA and SCL) with pull-up resistors and supports multi-master operation?
A
SPI (Serial Peripheral Interface)
B
I2C (Inter-Integrated Circuit)
C
UART / RS-232
D
CAN (Controller Area Network)
✓ Correct Answer: B - I2C (Inter-Integrated Circuit)
📖 Step-by-Step Solution & Conceptual Rationale:
I2C (invented by Philips/NXP) uses two wires: Serial Data (SDA) and Serial Clock (SCL), both pulled high by pull-up resistors, supporting addressing of multiple peripherals.
Sample Question 10
Microprocessors & Embedded Systems
Easy • Electronics Engineering
Which serial interface is synchronous, full-duplex, and uses four lines: MOSI, MISO, SCK, and SS/CS?
A
SPI (Serial Peripheral Interface)
B
I2C
C
RS-485
D
1-Wire
✓ Correct Answer: A - SPI (Serial Peripheral Interface)
📖 Step-by-Step Solution & Conceptual Rationale:
SPI operates with 4 signals: Master Out Slave In (MOSI), Master In Slave Out (MISO), Serial Clock (SCK), and Slave Select (SS), offering high data throughput with low protocol overhead.
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