Q. 1
Electronics Engineering
Difficulty: Easy
(1 Mark)
A Field Effect Transistor (FET) differs fundamentally from a BJT because a FET is a:
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Step-by-Step Explanation & Concept Rationale
BJTs are current-controlled and involve both majority and minority carriers (bipolar). FETs are voltage-controlled (gate voltage VGS modulates channel conductivity) and current flows via only one carrier type (electrons in N-channel, holes in P-channel), making them unipolar with ultra-high input impedance.
Q. 2
Electronics Engineering
Difficulty: Easy
(1 Mark)
The input impedance of a Junction Field Effect Transistor (JFET) gate is exceptionally high (typically 10^8 to 10^10 ohms) because:
💡
Step-by-Step Explanation & Concept Rationale
Under normal operation, the gate-channel PN junction is reverse-biased (VGS <= 0 for N-channel JFET). Only tiny reverse leakage current (nanoamperes) flows, yielding input resistance in hundreds of megaohms.
Q. 3
Electronics Engineering
Difficulty: Medium
(1 Mark)
In an N-channel JFET, the Pinch-off Voltage (Vp) is the value of drain-to-source voltage (VDS) at which:
💡
Step-by-Step Explanation & Concept Rationale
At pinch-off (VDS = |Vp|), the reverse bias at the drain end of the channel narrows the conductive channel to a constant constricted constriction. Electrons are swept through by the electric field, keeping drain current saturated and constant at IDSS (saturation/active region).
Q. 4
Electronics Engineering
Difficulty: Easy
(1 Mark)
Shockley's equation for the drain current ID of a JFET in the saturation (pinch-off) region is:
💡
Step-by-Step Explanation & Concept Rationale
Shockley's transfer equation states: ID = IDSS * [1 - (VGS / Vp)]^2, where IDSS is maximum drain current with VGS = 0, and Vp is pinch-off voltage (gate-source cutoff voltage VGS_off). It exhibits a non-linear square-law transfer characteristic.
Q. 5
Electronics Engineering
Difficulty: Medium
(1 Mark)
The transconductance (gm) of a JFET operating in saturation is mathematically derived as:
💡
Step-by-Step Explanation & Concept Rationale
Differentiating Shockley's equation with respect to VGS gives: gm = dID / dVGS = [2 * IDSS / |Vp|] * [1 - (VGS / Vp)] = gm0 * [1 - (VGS / Vp)]. Maximum transconductance gm0 occurs at VGS = 0.
Q. 6
Electronics Engineering
Difficulty: Medium
(1 Mark)
In the ohmic (triode) region where VDS < (VGS - Vp), a JFET behaves as a:
💡
Step-by-Step Explanation & Concept Rationale
At low VDS prior to pinch-off, drain current varies linearly with VDS: rDS = ro / [1 - (VGS / Vp)]. The JFET functions as a linear Voltage-Controlled Resistor, widely used in automatic gain control (AGC) circuits and analog multipliers.
Q. 7
Electronics Engineering
Difficulty: Easy
(1 Mark)
A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) has an input impedance significantly higher than a JFET (up to 10^12 to 10^14 ohms) because:
💡
Step-by-Step Explanation & Concept Rationale
The gate in a MOSFET is insulated by a thin layer of SiO2 (dielectric insulator with resistance > 10^14 ohms). Gate DC leakage current is virtually zero (picoamperes), giving it the highest input impedance of all solid-state transistors.
Q. 8
Electronics Engineering
Difficulty: Easy
(1 Mark)
An Enhancement-mode MOSFET (E-MOSFET) is classified as a 'normally-off' device because:
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Step-by-Step Explanation & Concept Rationale
In an N-channel E-MOSFET, the substrate between N+ source and drain is P-type. At VGS = 0, back-to-back PN junctions block current. Applying VGS > Vth attracts electrons to the surface, creating an N-type 'inversion layer' (channel). It is standard for digital logic.
Q. 9
Electronics Engineering
Difficulty: Medium
(1 Mark)
A Depletion-mode MOSFET (D-MOSFET) differs from an E-MOSFET because:
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Step-by-Step Explanation & Concept Rationale
D-MOSFETs have a built-in physical channel. Applying negative VGS depletes the channel of electrons (depletion mode), while applying positive VGS attracts more electrons, enhancing channel conductivity (enhancement mode).
Q. 10
Electronics Engineering
Difficulty: Medium
(1 Mark)
The drain current equation for an N-channel E-MOSFET in its saturation (active) region is given by:
💡
Step-by-Step Explanation & Concept Rationale
In saturation [VDS >= (VGS - Vth)], drain current follows square-law dependence: ID = (1/2) * k_n' * (W/L) * (VGS - Vth)^2, where Cox is gate oxide capacitance per unit area, and W/L is the transistor aspect ratio.
Q. 11
Electronics Engineering
Difficulty: Hard
(1 Mark)
In deep sub-micron MOSFETs, Channel Length Modulation refers to:
💡
Step-by-Step Explanation & Concept Rationale
Analogous to the Early Effect in BJTs, as VDS increases beyond saturation, the pinch-off point moves inward toward the source, shortening effective channel length. This increases drain current slightly: ID = ID_sat * (1 + lambda * VDS), where lambda is the channel-length modulation parameter.
Q. 12
Electronics Engineering
Difficulty: Hard
(1 Mark)
The Body Effect (substrate bias effect) in a MOSFET causes:
💡
Step-by-Step Explanation & Concept Rationale
When source-to-substrate voltage VSB > 0, the depletion layer between channel and substrate widens, exposing more bulk acceptor ions. A larger gate voltage is required to invert the channel, shifting threshold voltage: delta_Vth = gamma * [sqrt(2*phi_F + VSB) - sqrt(2*phi_F)].
Q. 13
Electronics Engineering
Difficulty: Easy
(1 Mark)
Why are N-channel MOSFETs (NMOS) faster and physically smaller than P-channel MOSFETs (PMOS) of identical current rating?
💡
Step-by-Step Explanation & Concept Rationale
Because carrier mobility for electrons is ~3 times greater than for holes, an NMOS transistor has roughly 3 times higher transconductance and drain current for the same W/L aspect ratio. To match NMOS drive strength in CMOS gates, PMOS width Wp must be designed 2 to 3 times wider than Wn.
Q. 14
Electronics Engineering
Difficulty: Easy
(1 Mark)
A basic CMOS (Complementary MOS) inverter consists of:
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Step-by-Step Explanation & Concept Rationale
CMOS logic combines complementary N-channel and P-channel enhancement MOSFETs. When input is HIGH (logic 1), NMOS conducts and PMOS is OFF (output = 0). When input is LOW (logic 0), PMOS conducts and NMOS is OFF (output = 1). In either steady state, one transistor is completely OFF.
Q. 15
Electronics Engineering
Difficulty: Easy
(1 Mark)
The primary technological advantage of CMOS logic over NMOS or TTL logic is:
💡
Step-by-Step Explanation & Concept Rationale
Because one transistor is always non-conducting in steady-state, static current is limited to minute leakage (nanoamperes). Power is consumed almost entirely during digital switching transitions (dynamic power: P_dyn = C * VDD^2 * f), making CMOS optimal for VLSI processors.
Q. 16
Electronics Engineering
Difficulty: Hard
(1 Mark)
The phenomenon of 'Latch-up' in CMOS integrated circuits refers to:
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Step-by-Step Explanation & Concept Rationale
CMOS structures naturally create parasitic vertical PNP and lateral NPN bipolar transistors forming a p-n-p-n thyristor structure. Voltage spikes or ionizing radiation can trigger regenerative regenerative latch-up, creating a low-impedance short between power rails that destroys the IC unless guard rings and substrate taps are placed.
Q. 17
Electronics Engineering
Difficulty: Easy
(1 Mark)
Why must discrete MOSFET devices and CMOS ICs be handled with grounded wrist straps and conductive anti-static bags?
💡
Step-by-Step Explanation & Concept Rationale
The gate oxide is extraordinarily thin (breakdown electric field ~10 MV/cm, equivalent to < 20-50 V across a 20 nm gate). Human static charges easily exceed thousands of volts, causing instantaneous dielectric rupture unless ESD protection clamps are in place.
Q. 18
Electronics Engineering
Difficulty: Medium
(1 Mark)
A Transmission Gate (analog bilateral switch) in CMOS circuits is formed by connecting:
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Step-by-Step Explanation & Concept Rationale
An NMOS passes a strong '0' but a degraded '1' (due to Vth loss); a PMOS passes a strong '1' but a degraded '0'. Connecting NMOS and PMOS in parallel with complementary clock signals (CLK and CLK_bar) passes full rail-to-rail analog voltages (0 to VDD) bidirectionally without threshold loss.
Q. 19
Electronics Engineering
Difficulty: Hard
(1 Mark)
The Drain-induced Barrier Lowering (DIBL) effect in short-channel MOSFETs results in:
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Step-by-Step Explanation & Concept Rationale
In short-channel devices (channel length < 100 nm), high drain voltage VDS creates a large depletion region that reaches close to the source, lowering the electrostatic potential barrier for electrons without gate assistance, causing subthreshold leakage current to surge.
Q. 20
Electronics Engineering
Difficulty: Medium
(1 Mark)
In power electronics, why do Power MOSFETs have a positive temperature coefficient of on-resistance (RDS_on)?
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Step-by-Step Explanation & Concept Rationale
Unlike BJTs (which have a negative temp coefficient leading to hot-spot current hogging), Power MOSFETs have positive temp coefficient: hotter transistors exhibit higher RDS_on, naturally shedding current to cooler parallel devices, making paralleling inherently safe.
Q. 21
Electronics Engineering
Difficulty: Easy
(1 Mark)
An Insulated Gate Bipolar Transistor (IGBT) combines the advantages of which two semiconductor devices?
💡
Step-by-Step Explanation & Concept Rationale
An IGBT possesses a MOS gate structure driving an internal bipolar p-n-p-n structure. It requires minimal gate drive power like a MOSFET, while its conductivity modulation in the drift region yields low on-state voltage drop (VCE_sat) like a BJT, dominating medium-to-high power inverters (up to 6.5 kV).
Q. 22
Electronics Engineering
Difficulty: Hard
(1 Mark)
A major switching limitation of an IGBT during turn-off is the 'Current Tail' caused by:
💡
Step-by-Step Explanation & Concept Rationale
When gate voltage drops below threshold, the internal MOSFET channel closes immediately. However, minority carriers trapped in the open base of the internal PNP transistor must recombine naturally without an external base terminal, producing a persistent current tail that increases turn-off switching losses.
Q. 23
Electronics Engineering
Difficulty: Medium
(1 Mark)
In a Common Source (CS) JFET amplifier with an unbypassed source resistor RS, the voltage gain is given by:
💡
Step-by-Step Explanation & Concept Rationale
The unbypassed source resistor RS introduces negative current-series feedback. Small signal analysis yields Av = -gm * RD / (1 + gm * RS). When RS is bypassed by a source capacitor CS, Av restores to -gm * RD.
Q. 24
Electronics Engineering
Difficulty: Hard
(1 Mark)
FinFET (3D Fin Field Effect Transistor) architecture was introduced in modern advanced semiconductor nodes (< 22 nm) primarily to:
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Step-by-Step Explanation & Concept Rationale
In planar MOSFETs below 22 nm, short-channel effects cause severe subthreshold leakage. FinFET's 3D fin wrapped by the gate on three sides provides tight electrostatic containment of the channel, drastically reducing off-state leakage and allowing scaling down to 3 nm.
Q. 25
Electronics Engineering
Difficulty: Hard
(1 Mark)
High Electron Mobility Transistors (HEMT / MODFET) fabricated from GaN or GaAs heterostructures achieve ultra-high microwave switching frequencies because:
💡
Step-by-Step Explanation & Concept Rationale
By spatially separating donor dopants from the conductive channel using an AlGaN/GaN heterojunction, a 2DEG sheet of electrons is formed. Without impurity collision scattering, electron mobility exceeds 2000 cm^2/V-s, enabling amplification at tens to hundreds of gigahertz in radar and 5G base stations.
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