FET & MOSFET
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📘 Comprehensive Syllabus & Examination Guide
FET & MOSFET
Official curriculum roadmap, subject/topic distribution, negative marking rules, pacing guidelines, and solved sample questions.
🎯 Mapped Subjects & Topic Question Distribution
Total Question Pool
100%
25 MCQs
Combined Active Syllabus
FET & MOSFET
25 MCQs
Topic Pool
📊 Question Pool Structure
25 MCQs across fundamental, intermediate, and advanced concept tiers.
⚡ Recommended Pacing
45 to 60 seconds per MCQ. Flag complex problems and preserve 10 minutes for final revision.
⚖️ Scoring & Negative Marking
+1 mark per correct answer. In competitive tests with negative marking, -0.25 applies for incorrect guesses.
💡 Strategic Preparation & Exam Hall Guidelines
To maximize your score on FET & MOSFET, candidates are advised to follow a structured three-pass approach. In the First Pass, solve all direct recall and formula-based questions within 30 seconds each to secure foundational marks. In the Second Pass, tackle multi-step analytical and quantitative reasoning problems. In the Third Pass, review marked questions and verify calculations.
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Solved Blueprint Examples
Showing 10 solved representative questions
📝 Pre-Rendered Solved Sample Questions & Detailed Solutions
Review the solved problems below to understand question phrasing, answer choices, and step-by-step solution logic prior to starting the full interactive practice drill:
Sample Question 1
FET & MOSFET
Easy • Electronics Engineering
A Field Effect Transistor (FET) differs fundamentally from a BJT because a FET is a:
A
Unipolar, voltage-controlled device where current conduction is mediated solely by majority carriers
B
Bipolar, current-controlled device
C
Device with very low input impedance
D
Device that cannot amplify high frequencies
✓ Correct Answer: A - Unipolar, voltage-controlled device where current conduction is mediated solely by majority carriers
📖 Step-by-Step Solution & Conceptual Rationale:
BJTs are current-controlled and involve both majority and minority carriers (bipolar). FETs are voltage-controlled (gate voltage VGS modulates channel conductivity) and current flows via only one carrier type (electrons in N-channel, holes in P-channel), making them unipolar with ultra-high input impedance.
Sample Question 2
FET & MOSFET
Easy • Electronics Engineering
The input impedance of a Junction Field Effect Transistor (JFET) gate is exceptionally high (typically 10^8 to 10^10 ohms) because:
A
The Gate-to-Source PN junction is always operated under reverse bias
B
The gate is made of thick gold
C
The channel is insulated by air
D
The drain is grounded
✓ Correct Answer: A - The Gate-to-Source PN junction is always operated under reverse bias
📖 Step-by-Step Solution & Conceptual Rationale:
Under normal operation, the gate-channel PN junction is reverse-biased (VGS <= 0 for N-channel JFET). Only tiny reverse leakage current (nanoamperes) flows, yielding input resistance in hundreds of megaohms.
Sample Question 3
FET & MOSFET
Medium • Electronics Engineering
In an N-channel JFET, the Pinch-off Voltage (Vp) is the value of drain-to-source voltage (VDS) at which:
A
The depletion layers touch across the channel, causing drain current to saturate at a constant maximum value (IDSS) for VGS = 0
B
The gate junction breaks down irreversibly
C
Drain current drops to zero
D
The device acts as an open circuit
✓ Correct Answer: B - The gate junction breaks down irreversibly
📖 Step-by-Step Solution & Conceptual Rationale:
At pinch-off (VDS = |Vp|), the reverse bias at the drain end of the channel narrows the conductive channel to a constant constricted constriction. Electrons are swept through by the electric field, keeping drain current saturated and constant at IDSS (saturation/active region).
Sample Question 4
FET & MOSFET
Easy • Electronics Engineering
Shockley's equation for the drain current ID of a JFET in the saturation (pinch-off) region is:
A
ID = IDSS * [1 - (VGS / Vp)]^2
B
ID = IDSS * [1 - (VGS / Vp)]
C
ID = IDSS * (VGS / Vp)^2
D
ID = beta * VGS
✓ Correct Answer: A - ID = IDSS * [1 - (VGS / Vp)]^2
📖 Step-by-Step Solution & Conceptual Rationale:
Shockley's transfer equation states: ID = IDSS * [1 - (VGS / Vp)]^2, where IDSS is maximum drain current with VGS = 0, and Vp is pinch-off voltage (gate-source cutoff voltage VGS_off). It exhibits a non-linear square-law transfer characteristic.
Sample Question 5
FET & MOSFET
Medium • Electronics Engineering
The transconductance (gm) of a JFET operating in saturation is mathematically derived as:
A
gm = gm0 * [1 - (VGS / Vp)], where gm0 = 2 * IDSS / |Vp|
B
gm = IDSS / Vp
C
gm = Vp / IDSS
D
gm = 2 * IDSS * VGS
✓ Correct Answer: A - gm = gm0 * [1 - (VGS / Vp)], where gm0 = 2 * IDSS / |Vp|
📖 Step-by-Step Solution & Conceptual Rationale:
Differentiating Shockley's equation with respect to VGS gives: gm = dID / dVGS = [2 * IDSS / |Vp|] * [1 - (VGS / Vp)] = gm0 * [1 - (VGS / Vp)]. Maximum transconductance gm0 occurs at VGS = 0.
Sample Question 6
FET & MOSFET
Medium • Electronics Engineering
In the ohmic (triode) region where VDS < (VGS - Vp), a JFET behaves as a:
A
Voltage-Controlled Resistor (VCR) whose channel resistance is modulated by gate voltage VGS
B
Constant current source
C
High-frequency diode detector
D
Negative resistance oscillator
✓ Correct Answer: A - Voltage-Controlled Resistor (VCR) whose channel resistance is modulated by gate voltage VGS
📖 Step-by-Step Solution & Conceptual Rationale:
At low VDS prior to pinch-off, drain current varies linearly with VDS: rDS = ro / [1 - (VGS / Vp)]. The JFET functions as a linear Voltage-Controlled Resistor, widely used in automatic gain control (AGC) circuits and analog multipliers.
Sample Question 7
FET & MOSFET
Easy • Electronics Engineering
A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) has an input impedance significantly higher than a JFET (up to 10^12 to 10^14 ohms) because:
A
The metallic gate electrode is completely physically and electrically isolated from the semiconductor channel by an ultra-thin silicon dioxide (SiO2) dielectric layer
B
The gate PN junction has zero leakage
C
It operates in liquid nitrogen
D
Electrons cannot cross silicon
✓ Correct Answer: A - The metallic gate electrode is completely physically and electrically isolated from the semiconductor channel by an ultra-thin silicon dioxide (SiO2) dielectric layer
📖 Step-by-Step Solution & Conceptual Rationale:
The gate in a MOSFET is insulated by a thin layer of SiO2 (dielectric insulator with resistance > 10^14 ohms). Gate DC leakage current is virtually zero (picoamperes), giving it the highest input impedance of all solid-state transistors.
Sample Question 8
FET & MOSFET
Easy • Electronics Engineering
An Enhancement-mode MOSFET (E-MOSFET) is classified as a 'normally-off' device because:
A
No physical conductive channel exists at VGS = 0; current cannot flow until gate voltage exceeds a positive Threshold Voltage (VGS > Vth) to create an inversion layer
B
It requires negative gate bias to conduct
C
The channel is permanently depleted
D
The source is disconnected
✓ Correct Answer: A - No physical conductive channel exists at VGS = 0; current cannot flow until gate voltage exceeds a positive Threshold Voltage (VGS > Vth) to create an inversion layer
📖 Step-by-Step Solution & Conceptual Rationale:
In an N-channel E-MOSFET, the substrate between N+ source and drain is P-type. At VGS = 0, back-to-back PN junctions block current. Applying VGS > Vth attracts electrons to the surface, creating an N-type 'inversion layer' (channel). It is standard for digital logic.
Sample Question 9
FET & MOSFET
Medium • Electronics Engineering
A Depletion-mode MOSFET (D-MOSFET) differs from an E-MOSFET because:
A
It has a physically fabricated channel and can operate in both Depletion mode (negative VGS) and Enhancement mode (positive VGS)
B
It cannot conduct current under positive gate bias
C
It has zero breakdown voltage
D
It has no gate insulator
✓ Correct Answer: A - It has a physically fabricated channel and can operate in both Depletion mode (negative VGS) and Enhancement mode (positive VGS)
📖 Step-by-Step Solution & Conceptual Rationale:
D-MOSFETs have a built-in physical channel. Applying negative VGS depletes the channel of electrons (depletion mode), while applying positive VGS attracts more electrons, enhancing channel conductivity (enhancement mode).
Sample Question 10
FET & MOSFET
Medium • Electronics Engineering
The drain current equation for an N-channel E-MOSFET in its saturation (active) region is given by:
A
ID = k * (VGS - Vth)^2 = (1/2) * mu_n * Cox * (W / L) * (VGS - Vth)^2
B
ID = k * (VGS - Vth)
C
ID = IDSS * (1 - VGS/Vth)
D
ID = VDS / (VGS - Vth)
✓ Correct Answer: A - ID = k * (VGS - Vth)^2 = (1/2) * mu_n * Cox * (W / L) * (VGS - Vth)^2
📖 Step-by-Step Solution & Conceptual Rationale:
In saturation [VDS >= (VGS - Vth)], drain current follows square-law dependence: ID = (1/2) * k_n' * (W/L) * (VGS - Vth)^2, where Cox is gate oxide capacitance per unit area, and W/L is the transistor aspect ratio.
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