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Microcontrollers & Embedded Architectures (Electronics Engineering) Solved Questions & Notes (2026) - Apex Rankers

Engineering & Technology > Electronics Engineering > Microcontrollers & Embedded Architectures

61 Total Solved Questions
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Microcontrollers & Embedded Architectures

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Q. 1 Electronics Engineering
Difficulty: medium (1 Mark)
In ARM Cortex-M microcontrollers (e.g., Cortex-M4), what is the function of the Nested Vectored Interrupt Controller (NVIC)?
A
To regulate the 3.3V DC core power supply voltage
B
To convert analog sensor voltages into digital values
C
To perform floating-point square root calculations in hardware
D
To manage low-latency hardware interrupt handling, nested priority preemption, and automatic register state saving
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
The NVIC in ARM Cortex-M processors provides dynamic priority grouping, hardware tail-chaining, nested interrupt preemption, and low-latency interrupt dispatching with automatic stacking of R0-R3, R12, LR, PC, and xPSR.
Q. 2 Electronics Engineering
Difficulty: hard (1 Mark)
What is 'Tail-Chaining' in ARM Cortex-M interrupt architecture?
A
Cascading timer prescalers in series
B
Appending checksum bytes to the end of a UART message
C
A mechanism where a pending interrupt executes immediately after the current ISR finishes WITHOUT popping and re-pushing the CPU register stack, reducing interrupt latency to as little as 6 clock cycles
✓ Correct
D
Connecting multiple microcontrollers in a daisy-chain serial loop
💡 Step-by-Step Explanation & Concept Rationale
Tail-chaining allows the processor to transition from one ISR to another pending ISR without unstacking and restacking core registers, significantly speeding up interrupt servicing.
Q. 3 Electronics Engineering
Difficulty: easy (1 Mark)
In Harvard Architecture microcontrollers (such as AVR and PIC), how are memory buses structured compared to von Neumann architecture?
A
Program memory and Data memory share a single common multiplexed bus
B
There is no RAM; all variables are stored in CPU registers
C
Data memory is stored exclusively on external SPI EEPROM chips
D
Program memory (Flash/ROM) and Data memory (SRAM) have separate physical address and data buses, allowing simultaneous instruction fetch and data access in a single clock cycle
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Harvard architecture uses separate buses and memory spaces for code and data, eliminating the von Neumann bottleneck and enabling single-cycle pipelined instruction execution.
Q. 4 Electronics Engineering
Difficulty: easy (1 Mark)
What is the primary role of a Direct Memory Access (DMA) controller in embedded microcontroller systems?
A
To execute arithmetic instructions faster than the ALU
B
To generate hardware PWM waveforms for motor control
C
To transfer high-speed data blocks directly between peripherals (e.g., ADC, SPI, UART) and SRAM memory without loading or interrupting the CPU core during every byte transfer
✓ Correct
D
To measure supply voltage variations
💡 Step-by-Step Explanation & Concept Rationale
DMA offloads repetitive data movement from the CPU core, freeing processing power for application logic and signal processing while peripherals stream data directly to/from memory buffers.
Q. 5 Electronics Engineering
Difficulty: hard (1 Mark)
In a circular DMA buffer configuration receiving continuous ADC telemetry data, how does the firmware prevent buffer overrun and data corruption?
A
By disabling all peripheral clocks during data reception
B
By setting the CPU clock frequency to zero
C
By deleting the first half of the array automatically
D
By utilizing Half-Transfer Complete (HT) and Transfer Complete (TC) interrupts (Ping-Pong double buffering)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Ping-Pong double buffering uses the Half-Transfer interrupt to process the first half of the buffer while the DMA fills the second half, and the Transfer-Complete interrupt to process the second half while DMA wraps around to refill the first half.
Q. 6 Electronics Engineering
Difficulty: easy (1 Mark)
What is the purpose of a 'Watchdog Timer' (WDT) in embedded safety-critical systems?
A
To keep track of the real-time calendar date and hour
B
To clock the external crystal oscillator
C
To measure the pulse width of incoming PWM signals
D
To automatically reset or recover the microcontroller if the software execution gets stuck in an infinite hang loop or crashes due to electrostatic discharge (ESD)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
A Watchdog Timer is a hardware down-counter clocked by an independent internal RC oscillator; firmware must periodically 'pet' (refresh) the watchdog, otherwise it times out and triggers a hardware system reset.
Q. 7 Electronics Engineering
Difficulty: hard (1 Mark)
What is a 'Windowed Watchdog Timer' (WWDG) and how does it provide enhanced safety over a standard independent watchdog?
A
It operates only when a graphic display window is active
B
It has a transparent glass window on top of the silicon chip
C
It triggers a reset if refreshed too late (timeout) OR if refreshed TOO EARLY before a predefined time window opens, catching runaway code loops that execute too rapidly
✓ Correct
D
It can only be refreshed once per year
💡 Step-by-Step Explanation & Concept Rationale
A Windowed Watchdog enforces both an upper and a lower time bound: early refresh (caused by corrupted program counter jumping erratically over the refresh routine) triggers a fault reset just like a delayed refresh.
Q. 8 Electronics Engineering
Difficulty: hard (1 Mark)
In real-time embedded programming, what is 'Priority Inversion' and how does a Real-Time Operating System (RTOS) resolve it?
A
Inverting the logical polarity of GPIO output pins from active-high to active-low
B
Reversing the direction of current flow in an H-bridge driver
C
A low-priority task holds a shared mutex resource needed by a high-priority task, while a medium-priority task preempts the low-priority task; resolved using Priority Inheritance or Priority Ceiling protocols
✓ Correct
D
Sorting interrupt priorities in reverse numerical order
💡 Step-by-Step Explanation & Concept Rationale
Priority Inversion allows medium tasks to indefinitely delay high-priority tasks; Priority Inheritance temporarily elevates the low-priority task's priority to match the blocked high-priority task until it releases the mutex.
Q. 9 Electronics Engineering
Difficulty: hard (1 Mark)
What is the difference between a 'Binary Semaphore' and a 'Mutex' (Mutual Exclusion lock) in FreeRTOS / RTOS design?
A
A Mutex includes ownership tracking and priority inheritance to prevent priority inversion, whereas a Semaphore is a signaling mechanism with no ownership that can be given by any task or ISR
✓ Correct
B
A Semaphore uses hardware interrupts, while a Mutex uses analog voltage
C
A Mutex can hold counts up to 255, while a Semaphore is always binary
D
There is no difference; they are identical in machine code
💡 Step-by-Step Explanation & Concept Rationale
A Mutex has an owner (the task that took it must give it back, supporting priority inheritance). A Semaphore is used for synchronization (e.g., ISR signaling a worker task) and has no concept of ownership.
Q. 10 Electronics Engineering
Difficulty: easy (1 Mark)
What is 'Brown-Out Reset' (BOR / BOD) circuitry in microcontrollers?
A
A reset triggered when the PCB color changes to brown
B
A reset command sent over an RS-232 serial cable
C
A supervisor circuit that holds the microcontroller in reset when the $V_{DD}$ supply voltage drops below a minimum safe operating threshold, preventing memory corruption and erratic CPU execution
✓ Correct
D
A thermal circuit breaker that trips when the chip overheats
💡 Step-by-Step Explanation & Concept Rationale
When supply voltage dips below reliable CMOS switching levels, unpredictable instructions can execute and corrupt Flash/EEPROM; BOD forces a clean hardware reset until voltage stabilizes.
Q. 11 Electronics Engineering
Difficulty: medium (1 Mark)
In microcontroller Timer/Counter peripherals, what does 'Input Capture' mode accomplish?
A
It captures analog voltage levels using a successive approximation register
B
It records audio samples directly to an SD card
C
It locks the CPU clock frequency to prevent drift
D
It latches the instantaneous value of the free-running counter into a capture register upon detecting an edge (rising/falling) on an external GPIO pin, enabling precise frequency and pulse-width measurement
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Input capture timestamps external hardware transitions (e.g., tachometer pulses, ultrasonic echo returns) with sub-microsecond timer resolution without CPU polling latency.
Q. 12 Electronics Engineering
Difficulty: medium (1 Mark)
What is the formula for calculating the output PWM frequency $f_{PWM}$ of a microcontroller timer with clock frequency $f_{CLK}$, prescaler $PSC$, and auto-reload period value $ARR$ (in up-counting mode)?
A
$f_{PWM} = \frac{(PSC + 1)}{(ARR + 1)}$
B
$f_{PWM} = \frac{f_{CLK}}{PSC \times ARR}$
C
$f_{PWM} = f_{CLK} \times (PSC + 1) \times (ARR + 1)$
D
$f_{PWM} = \frac{f_{CLK}}{(PSC + 1) \times (ARR + 1)}$
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Timer hardware scales the input clock by dividing it by $(PSC + 1)$ to advance the counter, which overflows and resets after counting from 0 up to $ARR$, yielding frequency $f_{PWM} = \frac{f_{CLK}}{(PSC+1)(ARR+1)}$.
Q. 13 Electronics Engineering
Difficulty: medium (1 Mark)
What is 'Dead-Time Insertion' in advanced microcontroller PWM timers driving complementary Half-Bridge power MOSFETs?
A
The time required for an ADC conversion to complete
B
The time when the microcontroller enters sleep mode to save battery
C
A short programmable delay introduced between turning off one transistor and turning on the complementary transistor to prevent catastrophic 'Shoot-Through' short circuits across the DC bus
✓ Correct
D
The period during which the PWM duty cycle is exactly zero
💡 Step-by-Step Explanation & Concept Rationale
Because power MOSFETs have finite turn-off fall times ($t_f$), dead-time ensures the high-side switch is fully off before the low-side switch turns on, preventing destructive shoot-through currents.
Q. 14 Electronics Engineering
Difficulty: easy (1 Mark)
In RISC-V processor architectures, what is the base 32-bit integer instruction set denoted as?
A
RV64G
B
ARMv7-M
C
RV32E
D
RV32I
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
RV32I is the foundational standard 32-bit integer instruction set architecture of RISC-V, containing 32 general-purpose 32-bit registers (x0 to x31) and 47 base instructions.
Q. 15 Electronics Engineering
Difficulty: medium (1 Mark)
In embedded C programming for memory-mapped I/O registers, why must peripheral register pointers be declared with the `volatile` type qualifier?
A
To inform the compiler optimizer that the register value can change asynchronously outside the program flow (e.g., by hardware state or ISR), preventing the compiler from caching reads or eliminating writes
✓ Correct
B
To store the variable in non-volatile Flash memory rather than RAM
C
To make the variable accessible across multiple C source files
D
To encrypt the data bus against reverse engineering
💡 Step-by-Step Explanation & Concept Rationale
Without `volatile`, aggressive compiler optimization may read a hardware status register once into a CPU register and loop indefinitely on the cached copy, missing external hardware flag transitions.
Q. 16 Electronics Engineering
Difficulty: easy (1 Mark)
What is the function of the SysTick (System Tick) timer in ARM Cortex-M processors?
A
A timer used exclusively for measuring battery temperature
B
A dedicated 24-bit down-counting periodic timer integrated directly into the core, designed to generate regular time-slice interrupts for RTOS kernel schedulers
✓ Correct
C
A hardware multiplier for digital filter implementation
D
A high-frequency clock source for Ethernet MAC controllers
💡 Step-by-Step Explanation & Concept Rationale
SysTick is an integral part of the ARM Cortex-M core, providing a standardized, portable periodic interrupt (typically 1 ms) to drive RTOS context switches and OS timekeeping across all Cortex-M silicon vendors.
Q. 17 Electronics Engineering
Difficulty: medium (1 Mark)
What is 'Memory Protection Unit' (MPU) in embedded microcontrollers?
A
A physical metal enclosure shielding the Flash memory chip from X-rays
B
A cyclic redundancy check (CRC) coprocessor
C
A backup battery preserving SRAM contents during power loss
D
A hardware block that partitions memory into privileged/unprivileged zones and defines read/write/execute permissions, preventing faulty tasks or stack overflows from corrupting OS kernel structures
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
The MPU enforces memory access permissions (e.g., making OS code read-only, preventing user tasks from executing code from SRAM, catching stack overflow crashes), improving firmware fault isolation.
Q. 18 Electronics Engineering
Difficulty: hard (1 Mark)
What is 'Atomic Operation' in microcontroller hardware (e.g., `LDREX` / `STREX` instructions in ARM)?
A
An operation powered by a nuclear isotopic battery
B
An operation that resets the CPU core clock
C
An operation that executes completely without the possibility of being interrupted or interleaved by another thread or ISR, ensuring thread-safe read-modify-write synchronization
✓ Correct
D
An operation that splits 32-bit words into individual bits
💡 Step-by-Step Explanation & Concept Rationale
Load-Linked / Store-Conditional (or Exclusive Load/Store) provides hardware-level atomic synchronization primitives to implement lock-free queues, semaphores, and mutexes without disabling global interrupts.
Q. 19 Electronics Engineering
Difficulty: hard (1 Mark)
What is 'Bit-Banding' in ARM Cortex-M3 and Cortex-M4 architectures?
A
Grouping GPIO pins into 8-bit parallel ports
B
Compressing digital sensor data using Huffman coding
C
Binding two microcontrollers together using a ribbon cable
D
A memory-mapping feature that maps every single bit in designated SRAM and Peripheral regions to a unique 32-bit word address, enabling atomic single-cycle bit read/write operations without read-modify-write loops
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Bit-banding maps a 1-megabyte alias region to a 32-megabyte bit-band address space, allowing any individual peripheral register bit to be cleared or set with a single atomic 32-bit store instruction.
Q. 20 Electronics Engineering
Difficulty: medium (1 Mark)
In microcontroller GPIO architecture, what is the difference between 'Push-Pull' and 'Open-Drain' (Open-Collector) output modes?
A
Push-Pull actively drives both High (via P-MOS) and Low (via N-MOS); Open-Drain only actively drives Low (via N-MOS) and relies on an external pull-up resistor to float High, allowing wired-AND bus sharing (e.g., I2C)
✓ Correct
B
Push-Pull can only output 0V; Open-Drain outputs 5V
C
Push-Pull is an analog input mode; Open-Drain is a digital output mode
D
Open-Drain consumes twice as much power as Push-Pull
💡 Step-by-Step Explanation & Concept Rationale
Push-Pull drives both logic levels with low impedance. Open-Drain only pulls down to ground; when off, the pin is high-impedance, enabling multiple chips to share a single line with an external pull-up resistor without contention.
Q. 21 Electronics Engineering
Difficulty: easy (1 Mark)
What is the purpose of 'Internal Pull-Up / Pull-Down' resistors in microcontroller GPIO input pins?
A
To establish a known default logic level ($V_{DD}$ or $GND$) when the external pin is left floating or connected to an open switch, preventing spurious noise transitions and CMOS float currents
✓ Correct
B
To terminate high-speed differential transmission lines at 100 ohms
C
To measure the ambient room temperature
D
To limit current when charging an external electrolytic capacitor
💡 Step-by-Step Explanation & Concept Rationale
A floating CMOS gate has infinite input impedance and picks up stray electromagnetic noise, toggling uncontrollably; internal pull-ups (typically $20\text{ k}\Omega - 50\text{ k}\Omega$) guarantee a stable idle logic level.
Q. 22 Electronics Engineering
Difficulty: easy (1 Mark)
What is a 'Schmitt Trigger' input buffer integrated on microcontroller GPIO pins?
A
A comparator circuit with Hysteresis (different switching thresholds for rising and falling edges) that converts noisy, slow-moving analog signals into clean, chatter-free digital transitions
✓ Correct
B
A level shifter converting 5V logic to 1.8V logic
C
A thermal protection diode preventing overcurrent
D
A high-speed oscillator circuit for driving quartz crystals
💡 Step-by-Step Explanation & Concept Rationale
Schmitt triggers incorporate hysteresis ($V_{T+} > V_{T-}$), rejecting input voltage ripple and noise, preventing multiple false trigger edges when reading slow sensor signals or mechanical button presses.
Q. 23 Electronics Engineering
Difficulty: medium (1 Mark)
In microcontroller low-power modes (e.g., Sleep, Stop, Standby), how does 'Stop Mode' typically achieve ultra-low microamp power consumption?
A
By physically cutting the battery connection using a mechanical relay
B
By short-circuiting the power supply to ground
C
By running the CPU core at maximum frequency with zero instructions
D
By disabling the main CPU core and high-speed PLL/HSE oscillators while retaining SRAM contents and register states, wakeable via external interrupts or RTC alarm
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Stop mode powers down high-speed clock trees and the CPU core while keeping SRAM and register states preserved under low-power voltage regulation, drawing microamps while allowing fast microsecond wakeup.
Q. 24 Electronics Engineering
Difficulty: medium (1 Mark)
What is 'Standby Mode' in ultra-low-power microcontrollers (such as STM32L series)?
A
A state where only USB communication remains active
B
A state where the CPU operates at 1 MHz
C
A deep sleep state where the entire core, SRAM, and most peripherals are powered down, leaving only the Real-Time Clock (RTC) and backup registers active, drawing sub-microamp current
✓ Correct
D
A state where the display screen brightness is reduced by 50%
💡 Step-by-Step Explanation & Concept Rationale
Standby mode offers the lowest power consumption (nanoamps to sub-microamps) by cutting power to internal 1.2V domains and SRAM; waking up behaves like a cold system reset from a dedicated wakeup pin or RTC.
Q. 25 Electronics Engineering
Difficulty: easy (1 Mark)
What is 'Phase-Locked Loop' (PLL) in microcontroller clock generation circuitry?
A
A circuit that locks the phase angle of brushless DC motors
B
A feedback control circuit that multiplies a low-frequency crystal oscillator (e.g., 8 MHz) up to high internal CPU system frequencies (e.g., 72 MHz, 168 MHz, 480 MHz) with phase synchronization
✓ Correct
C
A hardware lock that prevents unauthorized access to Flash memory
D
An analog filter that removes high-frequency audio noise
💡 Step-by-Step Explanation & Concept Rationale
The PLL uses a phase detector, charge pump, loop filter, and Voltage-Controlled Oscillator (VCO) with frequency dividers to synthesize stable, high-speed system clocks from inexpensive external quartz crystals.
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