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FPGA, CPLD & VHDL / Verilog Design (Electronics Engineering) Solved Questions & Notes (2026) - Apex Rankers

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FPGA, CPLD & VHDL / Verilog Design

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Q. 1 Electronics Engineering
Difficulty: easy (1 Mark)
What is the fundamental building block used to implement arbitrary combinational Boolean logic functions in modern FPGAs?
A
Discrete transistor logic
B
Look-Up Table (LUT) with SRAM configuration memory
✓ Correct
C
AND-OR PLA array
D
Operational amplifier matrix
💡 Step-by-Step Explanation & Concept Rationale
Modern FPGAs implement combinational logic using $k$-input Look-Up Tables (LUTs, typically 4-LUT or 6-LUT), which store truth tables in small SRAM cells addressed by input logic lines.
Q. 2 Electronics Engineering
Difficulty: medium (1 Mark)
How many distinct Boolean logic functions of $K$ variables can be implemented by a single $K$-input Look-Up Table ($K$-LUT)?
A
$2^{2^K}$ functions
✓ Correct
B
$K^2$ functions
C
$2^K$ functions
D
$2K$ functions
💡 Step-by-Step Explanation & Concept Rationale
A $K$-input LUT contains $2^K$ configuration memory bits. Since each bit can be independently programmed to 0 or 1, the total number of realizable Boolean functions is $2^{2^K}$ (e.g., $2^{2^4} = 65,536$ for a 4-LUT; $2^{64} \approx 1.84 \times 10^{19}$ for a 6-LUT).
Q. 3 Electronics Engineering
Difficulty: medium (1 Mark)
What is the primary architectural difference between an FPGA and a CPLD (Complex Programmable Logic Device)?
A
CPLDs have millions of flip-flops while FPGAs have only tens
B
FPGAs use fine-grained SRAM-based Look-Up Tables (volatile, requiring external configuration flash at boot) with vast routing and high density; CPLDs use coarse-grained non-volatile Flash/EEPROM Macrocells with wide AND-OR arrays, providing instant-on operation and deterministic pin-to-pin propagation delays
✓ Correct
C
FPGAs cannot implement clock networks while CPLDs can
D
FPGAs process only analog signals while CPLDs process digital signals
💡 Step-by-Step Explanation & Concept Rationale
CPLDs feature non-volatile memory (instant-on, no boot EEPROM needed) and predictable, deterministic timing due to centralized switch matrices, whereas FPGAs provide massively higher logic capacity, BRAMs, and DSPs with segmented interconnect routing.
Q. 4 Electronics Engineering
Difficulty: easy (1 Mark)
In FPGA architecture, what components are typically contained within a Configurable Logic Block (CLB) or Logic Array Block (LAB)?
A
A high-voltage transformer and bridge rectifier
B
An analog audio synthesizer and speaker driver
C
An optical laser diode and photodiode
D
Multiple Look-Up Tables (LUTs), dedicated Flip-Flops/Latches, Carry Logic chains (for high-speed arithmetic adders), and wide multiplexers
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
A CLB (e.g., Xilinx Slice or Intel ALM) groups several LUTs with dedicated registers/flip-flops, high-speed carry lookahead chains for multi-bit addition, and fast multiplexer routing.
Q. 5 Electronics Engineering
Difficulty: medium (1 Mark)
What is the difference between 'Distributed RAM' and 'Block RAM' (BRAM) in an FPGA?
A
Distributed RAM operates only on analog signals
B
Distributed RAM is non-volatile while Block RAM is volatile
C
Block RAM is placed outside the FPGA chip on the PCB
D
Distributed RAM uses the SRAM cells inside logic LUTs (SliceM) for small, fast, multi-port local memory; Block RAM comprises dedicated, dual-port hard silicon SRAM blocks (e.g., 18Kb/36Kb) optimized for large data buffers and FIFOs
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Distributed RAM re-purposes LUT logic memory for small distributed tables (e.g., shallow FIFOs or shift registers), whereas dedicated BRAM columns provide megabits of high-density, dual-port static RAM without consuming logic LUTs.
Q. 6 Electronics Engineering
Difficulty: easy (1 Mark)
What dedicated mathematical function is performed by hardware 'DSP Slices' (e.g., Xilinx DSP48E1/E2) embedded in modern FPGAs?
A
Voltage regulation and DC-to-DC step-down conversion
B
High-speed Multiply-Accumulate (MAC) operations ($P = (A + D) \times B + C$) with pre-adders, multipliers, and ALU accumulators operating at hundreds of MHz
✓ Correct
C
Wi-Fi baseband antenna beam steering exclusively
D
Direct conversion of analog sound into MP3 audio
💡 Step-by-Step Explanation & Concept Rationale
Hardware DSP slices contain dedicated hardened high-speed multipliers (e.g., $18\times 25$ or $27\times 18$ bits) combined with 48-bit accumulators, enabling high-performance FIR filters, FFTs, and matrix math without burning generic logic fabric.
Q. 7 Electronics Engineering
Difficulty: easy (1 Mark)
What is the mathematical definition of 'Setup Time' ($t_{su}$) for a digital Flip-Flop?
A
The delay between the clock edge and the output $Q$ transition
B
The time required to boot the FPGA from power-on
C
The time it takes for the clock to travel from the crystal to the flip-flop
D
The minimum time interval before the active clock edge during which the data input $D$ must remain stable and unchanged
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Setup time $t_{su}$ is the required stability window prior to the clock edge to allow the internal master latch feedback loop to capture the incoming logic state reliably.
Q. 8 Electronics Engineering
Difficulty: easy (1 Mark)
What is the mathematical definition of 'Hold Time' ($t_h$) for a digital Flip-Flop?
A
The propagation delay through the combinational logic path
B
The total duration the clock signal remains high in each cycle
C
The minimum time interval after the active clock edge during which the data input $D$ must remain stable and unchanged
✓ Correct
D
The time the circuit can hold data without power
💡 Step-by-Step Explanation & Concept Rationale
Hold time $t_h$ guarantees that data does not change too soon after the clock edge, preventing the new data from blowing through the master latch while the latch is in the process of closing.
Q. 9 Electronics Engineering
Difficulty: easy (1 Mark)
In synchronous digital design, what is 'Metastability'?
A
An indeterminate state where a flip-flop output hovers at an intermediate voltage level between logic 0 and 1 or oscillates for an extended period when setup or hold timing constraints are violated
✓ Correct
B
The loss of power in the clock distribution network
C
The permanent physical destruction of silicon gates by overvoltage
D
A state where a flip-flop toggles at twice the clock frequency
💡 Step-by-Step Explanation & Concept Rationale
When an asynchronous input transitions within the setup/hold aperture ($t_{su}/t_h$), the internal bistable feedback cannot resolve instantaneously, causing output hovering/oscillation that resolves after an unpredictable duration.
Q. 10 Electronics Engineering
Difficulty: medium (1 Mark)
What is the standard hardware circuit used to mitigate metastability when synchronizing an asynchronous 1-bit control signal into a clock domain?
A
A Two-Flip-Flop (Dual-Rank) Synchronizer chain clocked by the destination clock domain
✓ Correct
B
A Schmitt trigger inverter placed in parallel
C
A high-value pull-up resistor connected to VCC
D
An analog RC low-pass filter with 10 ms time constant
💡 Step-by-Step Explanation & Concept Rationale
Cascading two D-flip-flops in series gives the first flip-flop an entire clock cycle $T_{clk}$ to resolve its metastable state before the stable resolved logic level is sampled by the second register.
Q. 11 Electronics Engineering
Difficulty: hard (1 Mark)
What is the formula for the Mean Time Between Failures (MTBF) of a two-stage flip-flop synchronizer?
A
$\text{MTBF} = 2^N \times t_{su}$
B
$\text{MTBF} = \tau \cdot T_W \cdot f_{clk}$
C
$\text{MTBF} = \frac{f_{clk} \cdot f_{data}}{t_r}$
D
$\text{MTBF} = \frac{e^{t_r / \tau}}{T_W \cdot f_{clk} \cdot f_{data}}$ (where $t_r$ is available resolving time, $\tau$ is latch settling time constant, $T_W$ is metastability window width)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
MTBF increases exponentially with available resolution time $t_r = T_{clk} - t_{su}$. At higher clock frequencies $f_{clk}$, adding a third synchronizer stage is often required to maintain MTBF in thousands of years.
Q. 12 Electronics Engineering
Difficulty: hard (1 Mark)
In Static Timing Analysis (STA), what is the formula for 'Setup Slack' along a register-to-register path?
A
$\text{Setup Slack} = t_h - t_{skew}$
B
$\text{Setup Slack} = \frac{T_{clk}}{2}$
C
$\text{Setup Slack} = t_{co} + t_{comb} - T_{clk}$
D
$\text{Setup Slack} = T_{clk} + t_{skew} - (t_{co} + t_{comb(max)} + t_{su})$ (Slack $\ge 0$ required for timing closure)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
For setup timing to pass without violation, the data arrival time ($t_{co} + t_{comb(max)}$) plus required setup time ($t_{su}$) must not exceed the data required time ($T_{clk} + t_{skew}$), yielding a non-negative Setup Slack.
Q. 13 Electronics Engineering
Difficulty: hard (1 Mark)
In Static Timing Analysis (STA), what is the formula for 'Hold Slack' along a register-to-register path?
A
$\text{Hold Slack} = T_{clk} - t_{comb(max)}$
B
$\text{Hold Slack} = T_{clk} / t_h$
C
$\text{Hold Slack} = t_{su} + t_{co}$
D
$\text{Hold Slack} = (t_{co(min)} + t_{comb(min)}) - (t_h + t_{skew})$ (Slack $\ge 0$ required to prevent hold violation)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Hold timing checks the fastest possible data propagation path ($t_{co(min)} + t_{comb(min)}$): it must arrive AFTER the hold time window ($t_h + t_{skew}$). Hold slack is independent of clock period $T_{clk}$ and cannot be fixed by lowering clock frequency!
Q. 14 Electronics Engineering
Difficulty: medium (1 Mark)
Why is a 'Hold Time Violation' considered more severe than a 'Setup Time Violation' in fabricated ASIC and FPGA silicon?
A
Hold violations cause the chip to physically overheat and melt
B
Hold violations corrupt non-volatile flash memory permanently
C
Hold violations invert the power supply polarity
D
Setup violations can be cured by simply reducing the clock frequency (increasing $T_{clk}$), whereas hold violations depend entirely on minimum path delays and cannot be resolved by changing clock frequency, rendering the chip permanently dysfunctional
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Because the hold condition $t_{co(min)} + t_{comb(min)} \ge t_h + t_{skew}$ does not contain $T_{clk}$, slowing down the system clock does NOT fix a hold violation; extra delay buffers must be physically inserted into the data path.
Q. 15 Electronics Engineering
Difficulty: easy (1 Mark)
What is 'Pipelining' in digital circuit design, and what is its primary effect on system performance?
A
Replacing all copper wires with optical fibers
B
Converting parallel data buses into serial UART streams
C
Combining multiple clock signals into a single clock
D
Inserting flip-flop register stages between chunks of combinational logic to break long critical paths, thereby increasing the maximum clock frequency ($f_{max}$) and throughput at the expense of adding latency cycles
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
By subdividing a long combinational path of delay $T$ into $N$ equal stages separated by registers, the new clock period becomes $T/N + t_{co} + t_{su}$, nearly multiplying maximum clock frequency by $N$ with $N$ clock cycles of latency.
Q. 16 Electronics Engineering
Difficulty: medium (1 Mark)
What is 'Clock Skew' ($t_{skew}$) in synchronous digital systems?
A
The rise time of the clock pulse from 10% to 90%
B
The duty cycle distortion of the crystal oscillator
C
The difference in clock arrival times at the clock inputs of two different flip-flops across the chip ($t_{skew} = t_{clk2} - t_{clk1}$)
✓ Correct
D
The random cycle-to-cycle variation in the clock period
💡 Step-by-Step Explanation & Concept Rationale
Clock skew is spatial timing variation caused by differences in clock tree wire routing lengths and buffer delays across the silicon die; positive skew helps setup time but harms hold time.
Q. 17 Electronics Engineering
Difficulty: medium (1 Mark)
What is 'Clock Jitter' in digital electronics?
A
The physical vibration of the PCB during operation
B
The delay of data through a multiplexer
C
The loss of clock signal amplitude over distance
D
The temporal variation / instability of the clock edges from their ideal periodic positions over time in the time domain (phase noise in frequency domain)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Jitter is short-term temporal variation in clock period or phase caused by thermal noise, power supply ripple, and substrate crosstalk, reducing the effective usable clock period for timing closure.
Q. 18 Electronics Engineering
Difficulty: medium (1 Mark)
What is a Mixed-Mode Clock Manager (MMCM) or Phase-Locked Loop (PLL) inside an FPGA used for?
A
Frequency synthesis (multiplying and dividing clock frequencies), clock de-skewing (zero-delay buffer mode), phase shifting, and jitter filtering across multiple internal clock trees
✓ Correct
B
Converting AC mains 220V into 1.2V DC
C
Storing large lookup tables for digital signal processing
D
Implementing asynchronous serial communication protocols
💡 Step-by-Step Explanation & Concept Rationale
MMCMs/PLLs lock internal feedback clocks to external reference oscillators, generating multiple synchronized phase-shifted and frequency-scaled system clocks while virtually eliminating internal clock tree insertion delay.
Q. 19 Electronics Engineering
Difficulty: easy (1 Mark)
What is the difference between a 'Moore' and a 'Mealy' Finite State Machine (FSM)?
A
A Moore FSM uses flip-flops while a Mealy FSM uses only resistors
B
A Moore FSM has no state transitions while Mealy has transitions
C
In a Moore FSM, the outputs depend solely on the Current State; in a Mealy FSM, the outputs depend on both the Current State AND the current inputs
✓ Correct
D
A Moore FSM operates only on rising edges while Mealy operates on falling edges
💡 Step-by-Step Explanation & Concept Rationale
Moore outputs change synchronously only when state registers update on clock edges (glitch-free). Mealy outputs can change immediately in response to input changes within the clock cycle, which may introduce combinational glitches.
Q. 20 Electronics Engineering
Difficulty: medium (1 Mark)
What are the characteristics of 'One-Hot' State Encoding in FPGA FSM implementation?
A
States are encoded in minimum-bit binary (e.g., 3 bits for 8 states)
B
Each state is assigned a dedicated flip-flop where exactly one flip-flop is '1' (hot) and all others are '0'; ideal for FPGAs because it simplifies next-state decoding logic into wide, fast LUT multiplexing
✓ Correct
C
State values increment by 2 in each clock cycle
D
All flip-flops toggle to '1' simultaneously
💡 Step-by-Step Explanation & Concept Rationale
FPGAs are rich in registers/flip-flops; One-Hot encoding uses $N$ flip-flops for $N$ states, eliminating complex multi-level decoding gates and yielding extremely fast next-state transition logic ($f_{max}$).
Q. 21 Electronics Engineering
Difficulty: hard (1 Mark)
What is 'Gray Code' state and counter encoding, and why is it mandatory for asynchronous FIFO read/write pointer crossing?
A
A compression algorithm that reduces file size by 50%
B
A code where all bits invert on every clock cycle
C
A code that uses shades of grey on graphical display monitors
D
A binary numerical system where consecutive values differ by exactly ONE bit at a time, preventing multi-bit transition race conditions and false intermediate codes when sampled across asynchronous clock domains
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
In binary counters, transitions like `0111` $\to$ `1000` toggle 4 bits simultaneously; if sampled across clock domains, bit skew causes transient invalid intermediate codes (e.g. `1111`). Gray code changes only 1 bit, guaranteeing sampled values are either old or new.
Q. 22 Electronics Engineering
Difficulty: hard (1 Mark)
In an Asynchronous FIFO design, how are the 'FIFO Full' and 'FIFO Empty' status flags generated reliably?
A
By counting clock pulses with a single shared 8-bit counter
B
By comparing the local write/read Gray-code pointer with the synchronized Gray-code pointer received from the opposite clock domain via dual-rank flip-flop synchronizers
✓ Correct
C
By measuring the analog charge on a capacitor
D
By reading the status byte over an I2C serial link
💡 Step-by-Step Explanation & Concept Rationale
Empty flag is evaluated in the read clock domain comparing read pointer to synchronized write pointer; Full flag is evaluated in write clock domain comparing write pointer to synchronized read pointer (with MSB inversions for wrap-around detection).
Q. 23 Electronics Engineering
Difficulty: easy (1 Mark)
In Verilog HDL, what is the critical behavioral difference between a 'Blocking Assignment' (`=`) and a 'Non-Blocking Assignment' (`<=`)?
A
Blocking is used only for clocks; Non-blocking is used only for reset
B
Blocking runs 10 times faster in physical hardware
C
Blocking synthesizes to flip-flops; Non-blocking synthesizes to wires only
D
Blocking (`=`) executes sequentially and immediately updates the variable before proceeding to the next statement; Non-blocking (`<=`) evaluates all right-hand expressions concurrently and schedules variable updates at the end of the simulation time step
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
In Verilog RTL design, non-blocking assignments (`<=`) MUST be used in sequential `always @(posedge clk)` blocks to accurately model simultaneous hardware register updates without simulation race conditions.
Q. 24 Electronics Engineering
Difficulty: easy (1 Mark)
What synthesis defect is created in Verilog when an `always @(*)` combinational block leaves some output signals unassigned in certain `if-else` or `case` branches?
A
A permanent short circuit to ground
B
A high-speed hardware multiplier
C
A digital phase-locked loop (PLL)
D
An unintended transparent Latch (inferred latch)
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
In combinational logic, if a signal is not assigned a value in all possible execution branches, the synthesizer is forced to create a physical latch to hold the signal's previous value, degrading timing and causing glitches.
Q. 25 Electronics Engineering
Difficulty: medium (1 Mark)
In VHDL, what is the difference between a `SIGNAL` and a `VARIABLE`?
A
A `SIGNAL` is digital while a `VARIABLE` is analog
B
A `SIGNAL` cannot be synthesized into FPGA logic
C
A `VARIABLE` can only store integer numbers
D
A `SIGNAL` represents physical hardware wiring/registers and updates after a delta simulation delay (using `<=`); a `VARIABLE` is local to a process, updates immediately with zero delay (using `:=`), and does not represent a physical wire
✓ Correct
💡 Step-by-Step Explanation & Concept Rationale
Signals represent inter-block interconnects and registered state evaluated concurrently across the architecture, while variables are sequential scratchpad holders scoped exclusively within a `process`, `function`, or `procedure`.
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