Official curriculum roadmap, subject/topic distribution, negative marking rules, pacing guidelines, and solved sample questions.
🎯 Mapped Subjects & Topic Question Distribution
Total Question Pool100%
14 MCQs
Combined Active Syllabus
PCB Inspection & Diagnostics
14 MCQs
Topic Pool
📊 Question Pool Structure
14 MCQs across fundamental, intermediate, and advanced concept tiers.
⚡ Recommended Pacing
45 to 60 seconds per MCQ. Flag complex problems and preserve 10 minutes for final revision.
⚖️ Scoring & Negative Marking
+1 mark per correct answer. In competitive tests with negative marking, -0.25 applies for incorrect guesses.
💡 Strategic Preparation & Exam Hall Guidelines
To maximize your score on PCB Inspection & Diagnostics, candidates are advised to follow a structured three-pass approach. In the First Pass, solve all direct recall and formula-based questions within 30 seconds each to secure foundational marks. In the Second Pass, tackle multi-step analytical and quantitative reasoning problems. In the Third Pass, review marked questions and verify calculations.
Practice with the interactive player below to evaluate your speed and accuracy under real exam pressure. Every question features full mathematical formulas, step-by-step worked solutions, and conceptual explanations vetted by Apex Rankers Academy subject matter specialists.
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Review the solved problems below to understand question phrasing, answer choices, and step-by-step solution logic prior to starting the full interactive practice drill:
In PCB manufacturing and quality inspection, what does the term 'tombstoning' refer to in surface-mount technology (SMT)?
AA chip component (resistor/capacitor) lifting on one end during reflow soldering due to unbalanced surface tension
BComplete delamination of inner copper planes
COxidation of gold plated edge contacts
DThermal runaway of power transistors
✓ Correct Answer:A - A chip component (resistor/capacitor) lifting on one end during reflow soldering due to unbalanced surface tension
📖 Step-by-Step Solution & Conceptual Rationale:
Tombstoning (the Manhattan effect) occurs when uneven heating or unequal solder pad geometry causes solder paste to melt faster on one end of a two-terminal chip component, pulling the component upright.
Which international standard specifies the acceptability criteria for electronic assemblies (soldering quality, component placement, cleanliness)?
AIPC-A-610
BISO 9001
CIEEE 802.3
DANSI C84.1
✓ Correct Answer:A - IPC-A-610
📖 Step-by-Step Solution & Conceptual Rationale:
IPC-A-610 ('Acceptability of Electronic Assemblies') is the internationally recognized benchmark standard for visual quality acceptance of soldered electronic assemblies (Class 1, Class 2, Class 3).
Electrostatic Discharge (ESD) generates transient potentials of thousands of volts that puncture the microscopic thin gate oxides (SiO2) of MOSFETs and CMOS ICs, causing latent or catastrophic failure.
To safely protect electronic components against ESD damage, an ESD wrist strap must incorporate which safety feature for the human operator?
AA 1-Megaohm current-limiting safety resistor in series with ground
BA direct zero-ohm copper braid connection to mains earth
CA 10-ampere fast-acting fuse
DA step-down isolating transformer
✓ Correct Answer:A - A 1-Megaohm current-limiting safety resistor in series with ground
📖 Step-by-Step Solution & Conceptual Rationale:
ESD wrist straps always include a series 1 Mohm resistor. This allows static charges to safely bleed off to earth in milliseconds while protecting the wearer against lethal electrical shock if they accidentally touch mains voltage.
In multilayer PCB design, what is the purpose of placing dedicated, unbroken ground and power planes adjacent to signal layers?
ATo increase PCB mechanical weight
BTo provide low-inductance return current paths, minimize loop area, and suppress EMI/crosstalk
CTo allow higher soldering temperatures during manual rework
DTo eliminate the need for surface-mount components
✓ Correct Answer:B - To provide low-inductance return current paths, minimize loop area, and suppress EMI/crosstalk
📖 Step-by-Step Solution & Conceptual Rationale:
Solid plane layers provide minimal impedance return paths directly beneath high-speed signal traces, minimizing current loop areas and dramatically reducing electromagnetic radiation (EMI) and crosstalk.
Because BGA solder balls are hidden underneath the component package body, X-ray inspection (AXI) is required to detect solder bridging, voids, cold solder joints, and missing balls.
Under RoHS directives banning lead (Pb), SAC305 (Sn96.5 Ag3.0 Cu0.5) is the most widely adopted lead-free solder alloy in surface mount manufacturing, with a melting point around 217°C.
What does JTAG (Joint Test Action Group - IEEE 1149.1) boundary-scan technology enable in modern electronic board testing?
ATesting of pin-to-pin interconnects, shorts, opens, and in-system programming of ICs without physical probe contact on pins
BMeasuring analog RF noise figure in microwave receivers
CIncreasing PCB trace current-carrying capacity by 200%
DGenerating clock signals for external switched-mode power supplies
✓ Correct Answer:A - Testing of pin-to-pin interconnects, shorts, opens, and in-system programming of ICs without physical probe contact on pins
📖 Step-by-Step Solution & Conceptual Rationale:
IEEE 1149.1 boundary-scan embeds shift-register cells at each I/O pin of ICs, allowing digital testing of continuity, traces, opens, and shorts, and firmware flashing via a simple 4- or 5-wire JTAG port.