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Digital Electronics (Electronics Engineering) Solved Questions & Notes (2026) - Apex Rankers

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Digital Electronics

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Q. 1 Electronics Engineering
Difficulty: Easy (1 Mark)
Which logic gates are classified as Universal Logic Gates because any Boolean logic function can be implemented using only that gate type?
A
NAND gate and NOR gate
✓ Correct
B
AND gate and OR gate
C
XOR gate and XNOR gate
D
NOT gate and BUFFER
💡 Step-by-Step Explanation & Concept Rationale
Both NAND and NOR gates are universal gates. By appropriate interconnection, NOT, AND, OR, XOR, XNOR, and all combinational and sequential logic circuits can be realized exclusively from NAND gates or exclusively from NOR gates.
Q. 2 Electronics Engineering
Difficulty: Easy (1 Mark)
According to De Morgan's First Law, the complement of a product of variables is equal to:
A
The sum of the individual complements: (A . B)' = A' + B'
✓ Correct
B
The product of the individual complements: (A . B)' = A' . B'
C
A + B
D
A' . B
💡 Step-by-Step Explanation & Concept Rationale
De Morgan's First Law states: (A . B)' = A' + B' (NAND gate is functionally equivalent to an active-low input Bubbled-OR gate). De Morgan's Second Law states: (A + B)' = A' . B' (NOR gate is equivalent to a Bubbled-AND gate).
Q. 3 Electronics Engineering
Difficulty: Easy (1 Mark)
What is the 2's complement representation of the decimal number -13 in an 8-bit signed binary format?
A
11110011
✓ Correct
B
11110010
C
00001101
D
10001101
💡 Step-by-Step Explanation & Concept Rationale
Decimal +13 in 8-bit binary is 00001101. Step 1: 1's complement (invert all bits) -> 11110010. Step 2: Add 1 -> 11110010 + 1 = 11110011.
Q. 4 Electronics Engineering
Difficulty: Easy (1 Mark)
The output of an Exclusive-OR (XOR) gate is HIGH (logic 1) when:
A
An odd number of its inputs are HIGH (modulo-2 addition)
✓ Correct
B
All inputs are HIGH simultaneously
C
All inputs are LOW simultaneously
D
An even number of inputs are HIGH
💡 Step-by-Step Explanation & Concept Rationale
For a 2-input XOR gate (Y = A'B + AB'): Y = 1 only when inputs are distinct (0,1 or 1,0). For multi-input XOR gates, output is 1 whenever the count of 1s at the input is odd, making XOR gates ideal for parity generators and binary adders.
Q. 5 Electronics Engineering
Difficulty: Easy (1 Mark)
A Half-Adder circuit adds two single-bit binary inputs A and B. The Boolean expressions for its Sum (S) and Carry (C) outputs are:
A
Sum = A XOR B, and Carry = A AND B
✓ Correct
B
Sum = A AND B, and Carry = A OR B
C
Sum = A XNOR B, and Carry = A NAND B
D
Sum = A + B, and Carry = A' . B
💡 Step-by-Step Explanation & Concept Rationale
In binary addition: 0+0=0 (S=0,C=0); 0+1=1 (S=1,C=0); 1+0=1 (S=1,C=0); 1+1=10 (S=0,C=1). This truth table corresponds exactly to Sum = A ⊕ B and Carry = A . B.
Q. 6 Electronics Engineering
Difficulty: Easy (1 Mark)
A Full-Adder circuit differs from a Half-Adder because:
A
It can add three binary bits simultaneously (inputs A, B, and Carry-in Cin from a previous stage)
✓ Correct
B
It contains internal flip-flops
C
It generates four output bits
D
It operates without clock pulses
💡 Step-by-Step Explanation & Concept Rationale
A half-adder cannot accept a carry from a lower-order stage. A full-adder accepts three inputs (A, B, Cin) and produces: Sum = A ⊕ B ⊕ Cin, and Carry_out = A.B + Cin.(A ⊕ B). A full-adder can be implemented using two half-adders and one OR gate.
Q. 7 Electronics Engineering
Difficulty: Easy (1 Mark)
A 4-variable Karnaugh Map (K-map) contains how many total cells?
A
16 cells
✓ Correct
B
8 cells
C
32 cells
D
4 cells
💡 Step-by-Step Explanation & Concept Rationale
A K-map for n variables contains 2^n minterm cells. For n = 4 variables (e.g., A, B, C, D), the map contains 2^4 = 16 cells arranged in Gray code order (00, 01, 11, 10) so adjacent cells differ by only a single bit.
Q. 8 Electronics Engineering
Difficulty: Medium (1 Mark)
Why are the row and column coordinates of a Karnaugh Map numbered in Gray Code sequence (00, 01, 11, 10) rather than standard binary sequence (00, 01, 10, 11)?
A
To ensure that adjacent physical cells (both horizontally and vertically) differ by only one variable complement, satisfying the Boolean minimization identity (x + x' = 1)
✓ Correct
B
To conserve silicon area
C
To allow decimal translation
D
To speed up computer simulation
💡 Step-by-Step Explanation & Concept Rationale
Gray code ensures unit distance adjacency (only one variable changes between neighboring cells). Grouping adjacent 1s into powers of two (2, 4, 8, 16) mathematically eliminates the variable that changes state according to A.B + A.B' = A.(B + B') = A.
Q. 9 Electronics Engineering
Difficulty: Easy (1 Mark)
A Multiplexer (MUX) is a digital combinational circuit that:
A
Selects one of many data input lines and routes it to a single output line based on binary select control inputs (Data Selector)
✓ Correct
B
Takes a single input and distributes it across multiple outputs
C
Converts binary to decimal
D
Stores digital words
💡 Step-by-Step Explanation & Concept Rationale
A multiplexer has 2^n data input lines, n select control lines, and 1 output line. For example, an 8-to-1 MUX has 8 inputs and 3 select lines (s2, s1, s0) to steer any selected input to the output.
Q. 10 Electronics Engineering
Difficulty: Medium (1 Mark)
How many 2-to-1 multiplexers are required to construct an 8-to-1 multiplexer?
A
7
✓ Correct
B
8
C
4
D
3
💡 Step-by-Step Explanation & Concept Rationale
Tree multiplexing uses 4 MUXes in the first stage (reducing 8 inputs to 4), 2 MUXes in the second stage (reducing 4 inputs to 2), and 1 MUX in the final stage (reducing 2 to 1). Total 2-to-1 MUXes required = 4 + 2 + 1 = 7.
Q. 11 Electronics Engineering
Difficulty: Easy (1 Mark)
In an S-R (Set-Reset) flip-flop, the invalid (indeterminate / forbidden) input condition occurs when:
A
S = 1 and R = 1 simultaneously
✓ Correct
B
S = 0 and R = 0
C
S = 1 and R = 0
D
S = 0 and R = 1
💡 Step-by-Step Explanation & Concept Rationale
In a NOR-latch SR flip-flop, setting S = 1 and R = 1 forces both outputs Q and Q' to zero simultaneously, violating the complementary nature of flip-flop outputs (Q != Q'). If inputs switch to 00 simultaneously, race conditions create an unpredictable final state.
Q. 12 Electronics Engineering
Difficulty: Easy (1 Mark)
How does a J-K flip-flop resolve the invalid state problem of an S-R flip-flop when both inputs are HIGH (J = 1 and K = 1)?
A
The output toggles (inverts) to its complementary state on each active clock pulse (Q_next = Q')
✓ Correct
B
The output latches into a permanent zero
C
The flip-flop burns out
D
The clock input is disabled
💡 Step-by-Step Explanation & Concept Rationale
In a JK flip-flop, outputs are cross-coupled back to the input AND gates. When J = 1 and K = 1, the flip-flop toggles its output on each clock pulse: Q_next = J.Q' + K'.Q = 1.Q' + 0.Q = Q'.
Q. 13 Electronics Engineering
Difficulty: Medium (1 Mark)
The 'Race-Around Condition' in a level-triggered J-K flip-flop occurs when:
A
J = 1, K = 1, and the clock pulse duration (tp) is longer than the propagation delay of the flip-flop (tpd), causing the output to oscillate repeatedly between 0 and 1 during a single clock pulse
✓ Correct
B
Clock frequency is too low
C
The power supply drops
D
Outputs are shorted
💡 Step-by-Step Explanation & Concept Rationale
If tp > tpd, the toggled output feeds back to the input while the clock is still high, toggling the output again and again uncontrollably. Race-around is eliminated by using Master-Slave flip-flop architecture, edge-triggering, or ensuring tp < tpd.
Q. 14 Electronics Engineering
Difficulty: Medium (1 Mark)
A Master-Slave J-K flip-flop eliminates the race-around condition by:
A
Cascading two flip-flops where the Master is enabled during the clock HIGH level, and the Slave is enabled on the inverted clock LOW level, transferring data only at clock transitions
✓ Correct
B
Removing internal feedback
C
Using high-speed ECL gates
D
Operating in continuous toggle mode
💡 Step-by-Step Explanation & Concept Rationale
The Master flip-flop samples inputs J and K while CLK is HIGH. The Slave is isolated by the inverter. When CLK transitions to LOW, the Master is disabled from input changes while the Slave reads the Master's state, preventing continuous feedback cycling.
Q. 15 Electronics Engineering
Difficulty: Easy (1 Mark)
A D (Data / Delay) flip-flop is created from a J-K flip-flop by connecting an inverter between J and K (K = J'). The characteristic equation is:
A
Q_next = D
✓ Correct
B
Q_next = D'
C
Q_next = Q
D
Q_next = D XOR Q
💡 Step-by-Step Explanation & Concept Rationale
A D flip-flop transfers the input bit D directly to output Q on the active clock edge (Q_next = D), providing a 1-clock-cycle delay. It is the fundamental building block of shift registers, RAM, and digital pipeline registers.
Q. 16 Electronics Engineering
Difficulty: Easy (1 Mark)
A T (Toggle) flip-flop is created from a J-K flip-flop by tying both inputs together (J = K = T). Its characteristic equation is:
A
Q_next = T XOR Q = T.Q' + T'.Q
✓ Correct
B
Q_next = T.Q
C
Q_next = T + Q
D
Q_next = T'
💡 Step-by-Step Explanation & Concept Rationale
When T = 0, the flip-flop holds its state (Q_next = Q). When T = 1, it toggles (Q_next = Q'). This Boolean function is Q_next = T ⊕ Q. Connecting T = 1 continuously divides the clock input frequency by exactly 2.
Q. 17 Electronics Engineering
Difficulty: Easy (1 Mark)
How many flip-flops (n) are required to construct a Modulo-N (Mod-N) asynchronous or synchronous binary counter?
A
2^n >= N
✓ Correct
B
n = N
C
n = 2 * N
D
n = N^2
💡 Step-by-Step Explanation & Concept Rationale
An n-bit binary counter can count through a maximum of 2^n unique states (from 0 to 2^n - 1). Therefore, to count modulo-N, the number of flip-flops n must satisfy 2^(n-1) < N <= 2^n (e.g., a Mod-10 decade counter requires n = 4 flip-flops because 2^3 = 8 < 10 <= 2^4 = 16).
Q. 18 Electronics Engineering
Difficulty: Medium (1 Mark)
In an Asynchronous (Ripple) Counter, the primary speed limitation is:
A
Cumulative propagation delay, because each flip-flop is clocked by the output of the preceding stage, causing delay to accumulate across all stages (t_total = n * tpd)
✓ Correct
B
Excessive power dissipation
C
Clock jitter in the crystal oscillator
D
High setup time
💡 Step-by-Step Explanation & Concept Rationale
In ripple counters, flip-flop stages do not switch simultaneously; the clock pulse ripples sequentially through the chain. Total delay is n * tpd. If n * tpd exceeds the clock period, decoding errors and false glitches occur, limiting maximum operating frequency.
Q. 19 Electronics Engineering
Difficulty: Easy (1 Mark)
In a Synchronous Counter, high operating speeds are achieved because:
A
All flip-flops are clocked simultaneously by the same master clock pulse
✓ Correct
B
Feedback loops are removed
C
Flip-flops operate on DC
D
It uses ECL gates only
💡 Step-by-Step Explanation & Concept Rationale
In a synchronous counter, the common clock is wired directly to the clock pins of every flip-flop. State transitions occur simultaneously across all bits in one single propagation delay (tpd), enabling much higher clock frequencies without ripple delay.
Q. 20 Electronics Engineering
Difficulty: Medium (1 Mark)
A Johnson Counter (twisted ring counter) constructed with n flip-flops possesses how many distinct states?
A
2 * n states
✓ Correct
B
n states
C
2^n states
D
n^2 states
💡 Step-by-Step Explanation & Concept Rationale
A Johnson counter feeds the inverted output of the last flip-flop (Qn') back into the input of the first flip-flop (D1). A 4-flip-flop Johnson counter circulates through 2 * n = 2 * 4 = 8 distinct states. A standard ring counter has only n states.
Q. 21 Electronics Engineering
Difficulty: Easy (1 Mark)
Which logic family provides the absolute HIGHEST switching speed (lowest propagation delay, < 1 ns)?
A
Emitter-Coupled Logic (ECL)
✓ Correct
B
Standard TTL (7400)
C
CMOS (4000 series)
D
NMOS
💡 Step-by-Step Explanation & Concept Rationale
ECL uses non-saturating BJT differential pairs operating in the active region. Because transistors never enter saturation, there is zero minority-carrier storage delay (ts = 0), allowing switching speeds well above several gigahertz, though at the expense of high continuous power dissipation.
Q. 22 Electronics Engineering
Difficulty: Easy (1 Mark)
The Fan-Out of a digital logic gate is defined as:
A
The maximum number of standard logic inputs of the same family that the output of the gate can reliably drive without degrading voltage logic levels
✓ Correct
B
The number of inputs connected to the gate
C
The cooling fan speed required for the IC
D
The propagation delay in nanoseconds
💡 Step-by-Step Explanation & Concept Rationale
Fan-out = min(IOH / IIH, IOL / IIL). It quantifies the load-driving capability of a digital gate while strictly preserving noise margins and legitimate logic-HIGH and logic-LOW voltage thresholds.
Q. 23 Electronics Engineering
Difficulty: Medium (1 Mark)
Noise Margin of a digital logic family is a measure of:
A
The maximum extraneous noise voltage that can be superimposed on an input signal without causing an erroneous change in the logic state (NMH = VOH - VIH, NML = VIL - VOL)
✓ Correct
B
Acoustic noise generated by switching
C
Power supply hum
D
Harmonic distortion in decibels
💡 Step-by-Step Explanation & Concept Rationale
High-level noise margin NMH = VOH_min - VIH_min, and low-level noise margin NML = VIL_max - VOL_max. Standard CMOS operating at 5 V has generous noise margins of ~1.5 V to 2.0 V (approx. 30-40% of VDD), far superior to TTL (~0.4 V).
Q. 24 Electronics Engineering
Difficulty: Easy (1 Mark)
In a 4-bit R-2R ladder Digital-to-Analog Converter (DAC), the total number of distinct resistor values required in the network is:
A
Only two values (R and 2R), regardless of the number of bits
✓ Correct
B
4 values (R, 2R, 4R, 8R)
C
16 values
D
8 values
💡 Step-by-Step Explanation & Concept Rationale
Unlike binary-weighted DACs (which require wide-ranging resistor values 2^n*R that are difficult to fabricate and match in silicon), an R-2R ladder requires only two precision resistance values (R and 2R), making it standard in high-resolution monolithic DAC ICs.
Q. 25 Electronics Engineering
Difficulty: Easy (1 Mark)
Which Analog-to-Digital Converter (ADC) architecture provides the FASTEST conversion time (single clock cycle)?
A
Flash (Parallel Comparator) ADC
✓ Correct
B
Successive Approximation Register (SAR) ADC
C
Dual-Slope Integrating ADC
D
Sigma-Delta (Delta-Sigma) ADC
💡 Step-by-Step Explanation & Concept Rationale
A Flash ADC uses 2^n - 1 simultaneous analog comparators comparing the input against a resistor ladder divider. Conversion occurs in a single clock cycle (< few nanoseconds). However, circuit complexity doubles with each added bit (an 8-bit flash ADC requires 255 comparators).
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